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Exploring a Design Space of 3-D Stacked Vector Processors

  • Ryusuke Egawa
  • Jubee Tada
  • Hiroaki Kobayashi
Conference paper

Abstract

Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.

Keywords

Integration Technology Memory Bandwidth Arithmetic Unit Phase Change Random Access Memory Vector Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

The authors would like to thank Associate Professor Hiroyuki Takizawa, Professor Mitsumasa Koyanagi of Tohoku University, Yusuke Funaya of Hitachi, Ryu-ichi Nagaoka of BOSCH, Dr. Akihiro Musa, Jun Inasaka and Dr. Shintaro Momose of NEC for valuable discussions on this research. This research was partially supported by Grant-in-Aid for Scientific Research (Grant-in-Aid for Young Scientists (B) No. 22 700044) and (Grant-in-Aid for Scientific Research (B) No. 22300013), the Ministry of Education, Culture, Sports, Science and Technology. This research was also partially supported by Core Research for Evolutional Science and Technology (CREST), Japan Science and Technology Agency (JST).

References

  1. 1.
    E. Beyne. Tsv technology overview. In Semicon Taiwan 2008 CTO Forum, 2008.Google Scholar
  2. 2.
    B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb. Die stacking (3d) microarchitecture. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 469–479, 2006.Google Scholar
  3. 3.
    S. Das, A. Fan, K.-N. Chen, C. S. Tan, N. Checka, and R. Reif. Technology, performance, and computer-aided design of three-dimensional integrated circuits. In ISPD ’04: Proceedings of the 2004 international symposium on Physical design, pages 108–115, New York, NY, USA, 2004. ACM.Google Scholar
  4. 4.
    W. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. Sule, M. Steer, and P. Franzon. Demystifying 3d ics: the pros and cons of going vertical. Design & Test of Computers, IEEE, 22(6):498–510, Nov.-Dec. 2005.Google Scholar
  5. 5.
    X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In DAC ’08: Proceedings of the 45th annual Design Automation Conference, pages 554–559, New York, NY, USA, 2008. ACM.Google Scholar
  6. 6.
    R. Egawa, Y. Funaya, R. Nagaoka, Y. Endo, A. Musa, H. Takizawat, and H. Kobayashi. Effects of 3-D Stacked Vector Cache on Energy Consumption. In 2011 IEEE International 3D Systems Integration Conference (3DIC), pages 1–8, 2012.Google Scholar
  7. 7.
    Y. Funaya, R. Egawa, H. Takizawat, and H. Kobayashi. 3D On-Chip Memory for the Vector Architecture. In 2009 IEEE International 3D Systems Integration Conference (3DIC), pages 1–8, 2009.Google Scholar
  8. 8.
    S. Gupta, M. Hilbert, , S. Hong, and R. Patti. Techniques for producing 3d ics with high-density interconnect. In Proceedings of the 21st International VLSI Multilevel Interconnection Conference, 2004.Google Scholar
  9. 9.
    J. Inasaka and M. Kajita. Techniques for power supply noise management in the SX supercomputers. In IEICE Tech. Report, pages 41–46, 2008.Google Scholar
  10. 10.
    T. Kgil, A. Saidi, N. Binkert, S. Reinhardt, K. Flautner, and T. Mudge. Picoserver: Using 3d stacking technology to build energy efficient servers. J. Emerg. Technol. Comput. Syst., 4(4):1–34, 2008.Google Scholar
  11. 11.
    D. Khalil, Y. Ismail, M. Khellah, T. Karnik, and V. De. Analytical model for the propagation delay of through silicon vias. In ISQED ’08: Proceedings of the 9th international symposium on Quality Electronic Design, pages 553–556, 2008.Google Scholar
  12. 12.
    M. Koyanagi, T. Fukushima, and T. Tanaka. High-density through silicon vias for 3-d lsis. Proceedings of the IEEE, 97(1):49–59, Jan. 2009.Google Scholar
  13. 13.
    M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino. Three-dimensional integration technology based on wafer bonding with vertical buried interconnections. IEEE Trans. Electron Devices, 53(11):2799–2808, 2006.Google Scholar
  14. 14.
    D. Kroft. Lockup-Free Instruction Fetch/Prefetch Cache Organization. ISCA, pages 81–88, 1981.Google Scholar
  15. 15.
    G. H. Loh. 3d-stacked memory architectures for multi-core processors. In ISCA ’08: Proceedings of the 35th International Symposium on Computer Architecture, pages 453–464, 2008.Google Scholar
  16. 16.
    G. H. Loh, Y. Xie, and B. Black. Processor Design in 3D Die-Stacking Technologies. IEEE Micro, 27(3):31–48, 2007.Google Scholar
  17. 17.
    G. H. Loh, Y. Xie, and B. Black. Processor Design in 3D Die-Stacking Technologies. Micro, IEEE, 27(3):31–48, may. 2007.Google Scholar
  18. 18.
    P. Marchal, B. Bougard, G. Katti, M. Stucchi, W. Dehaene, A. Papanikolaou, D. Verkest, B. Swinnen, and E. Beyne. 3-d technology assessment: Path-finding the technology/design sweet-spot. Proceedings of the IEEE, 97(1):96–107, Jan. 2009.Google Scholar
  19. 19.
    J. Mayega, O. Erdogan, P. M. Belemjian, K. Zhou, J. F. McDonald, and R. P. Kraft. 3d direct vertical interconnect microprocessors test vehicle. In GLSVLSI ’03: Proceedings of the 13th ACM Great Lakes symposium on VLSI, pages 141–146, New York, NY, USA, 2003. ACM.Google Scholar
  20. 20.
    N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. CACTI 6.5. Technical Report HPL-2009-85, HP Labs, 2009.Google Scholar
  21. 21.
    A. Musa, Y. Sato, R. Egawa, H. Takizawa, K. Okabe, and H. Kobayashi. An On-chip Cache Design for Vector Processors. In MEDEA ’07: Proceedings of the 2007 workshop on MEmory performance, pages 17–23, New York, NY, USA, 2007. ACM.Google Scholar
  22. 22.
    A. Musa, Y. Sato, T. Soga, K. Okabe, R. Egawa, H. Takizawa, and H. Kobayashi. A shared cache for a chip multi vector processor. In MEDEA ’08: Proceedings of the 9th workshop on MEmory performance, pages 24–29, New York, NY, USA, 2008. ACM.Google Scholar
  23. 23.
    J. S. Pak, C. Ryu, and J. Kim. Electrical characterization of trough silicon via (tsv) depending on structural and material parameters based on 3d full wave simulation. In Electronic Materials and Packaging, 2007. EMAP 2007. International Conference on, pages 1–6, Nov. 2007.Google Scholar
  24. 24.
    K. Puttaswamy and G. Loh. The impact of 3-dimensional integration on the design of arithmetic units. In Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS), pages 4951–4954, May 2006.Google Scholar
  25. 25.
    K. Puttaswamyt and G. H. Loh. Scalability of 3d-integrated arithmetic units in high-performance microprocessors. In DAC ’07: Proceedings of the 44th annual Design Automation Conference, pages 622–625, New York, NY, USA, 2007. ACM.Google Scholar
  26. 26.
    J. Tada, R. Egawa, K. Kawai, H. Kobayashi, and G. Goto. A Middle-Grain Circuit Partitioning Strategy for 3-D Integrated Floating-Point Multipliers. In 2011 IEEE International 3D Systems Integration Conference (3DIC), pages 1–8, 2012.Google Scholar
  27. 27.
    Y. Takagi, H. Sato, Y. Wagatsuma, K. Mizuno, and K. Sawaya. Study of High Gain and Broadband Antipodal Fermi Antenna with Corrugation. In 2004 International Symposium on Antennas and Propagation, pages 69–72, 2004.Google Scholar
  28. 28.
    Y.-F. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan, and M. J. Irwin. Design space exploration for 3-d cache. IEEE Trans. Very Large Scale Integr. Syst., 16(4):444–455, 2008.Google Scholar
  29. 29.
    B. Vaidyanathan, W.-L. Hung, F. Wang, Y. Xie, V. Narayanan, and M. J. Irwin. Architecting microprocessor components in 3d design space. In VLSID ’07: Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference, pages 103–108, Washington, DC, USA, 2007. IEEE Computer Society.Google Scholar
  30. 30.
    S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. In Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pages 98–589, feb. 2007.Google Scholar
  31. 31.
    X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie. Hybrid Cache Architecture with Disparate Memory Technologies. In ISCA ’09: Proceedings of the 36th annual international symposium on Computer architecture, pages 34–45, New York, NY, USA, 2009. ACM.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Cyberscience CenterTohoku University/JST CRESTSendaiJapan
  2. 2.Graduate School of Science and EngineeringYamagata UniversityYonezawaJapan

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