Design an Optimized CPU Architecture for Pacemaker Applications

Part of the IFMBE Proceedings book series (IFMBE, volume 49)

Abstract

The design technique of using gray code addressing to reduce power dissipation in CPU of pacemaker is presented in this paper. The experimental results of reducing power up to 20% would be a promising result. This work is implemented by using Altera Quartus II 9.0, the device Cylone II EP2C20F484C7 is used.

Keywords

Pacemaker CPU design low-power design Gray code addressing 

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Copyright information

© IFMBE 2013

Authors and Affiliations

  1. 1.University of Technology, Vietnam National University at HoChiMinh CityHoChiMinh CityVietnam

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