Fault Tolerant High Performance Galois Field Arithmetic Processor

  • Vinu K. Narayanan
  • Rishad A. Shafik
  • Jimson Mathew
  • Dhiraj K. Pradhan
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 305)


Reliability is an emerging design requirement for finite field processors used in cryptographic systems. However, reliable design of these systems is particularly challenging due to conflicting design requirements, including high performance and low power consumption. In this paper, we propose a novel design technique for reliable and low power Galois field (GF) arithmetic processor. The aim is to tolerate faults in the GF processor during on-line computation at reduced system costs, while maintaining high performance. The reduction in system costs is achieved through multiple parity prediction and comparison considering the trade-offs between performance and complexity. The effectiveness of the proposed technique is then validated using a case study of 163-bit digit serial multipliers using 90nm and 180nm technology nodes highlighting the resulting area, latency and power overheads. We show that up to 40 stuck-at faults can be tolerated during computation with reasonable system area and power costs.


Fault Tolerance Advanced Encryption Standard Very Large Scale Integration Area Overhead Galois Field 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Mastrovito, E.D.: VLSI Architectures for Computation in Galois Fields. PhD thesis, Linkoping University, Linkoping, Sweden (1991)Google Scholar
  2. 2.
    Deschamps, J.-P., Imana, J.L., Sutter, G.D.: Hardware implementation of Finite Field Arithmetic. The McGraw-Hill Companies Inc. (2009)Google Scholar
  3. 3.
    Blake, I., Seroussi, G., Smart, N.P.: Elliptic curves in cryptography. London Mathematical Society Lecture Note Series. Cambridge University Press, Cambridge (1999)zbMATHGoogle Scholar
  4. 4.
    Kumar, S., Wollinger, T., Paar, C.: Optimum Digit Serial GF(2m) Multipliers for Curve Based Cryptography. IEEE Transactions on Computers 55(10), 1306–1311 (2006)CrossRefGoogle Scholar
  5. 5.
    Orlando, G., Paar, C.: A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 41–56. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  6. 6.
    Pradhan, D.K.: Fault-Tolerant Computer System Design, 1st edn. Prentice-Hall, NJ (1996)Google Scholar
  7. 7.
    Johnson, B.W.: Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley (1989)Google Scholar
  8. 8.
    Fenn, S., Gossel, M., Benaissa, M., Taylor, D.: Online Error Detection for Bit-serial Multipliers in GF(2m). Journal of Electronic Testing: Theory and Applications 13, 29–40 (1998)CrossRefGoogle Scholar
  9. 9.
    Mathew, J., Singh, J., Jabir, A.M., Hosseinabady, M., Pradhan, D.K.: Fault Tolerant Bit Parallel Finite Field Multipliers using LDPC Codes. In: Proc. of ISCAS, pp. 1684–1687 (2008)Google Scholar
  10. 10.
    Gallager, R.: Low-Density Parity-Check Codes. MIT Press, Cambridge (1963)Google Scholar
  11. 11.
    Wu, K., Karri, R., Kuznetsov, G., Goessel, M.: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. In: Proceedings of ITC, pp. 1242–1248 (2004)Google Scholar
  12. 12.
    Bertoni, G., Breveglieri, L., Koren, I., Maistri, P., Piuri, V.: Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. IEEE Trans. on Computers, Special issue on Cryptographic Hardware and Embedded Systems 52(4), 492–505 (2003)Google Scholar
  13. 13.
    Reyhani-Masoleh, A., Hasan, M.A.: Fault Detection Architectures for Field Multiplication Using Polynomial Bases. IEEE Trans. on Computers 55(9) (September 2006)Google Scholar
  14. 14.
    Meher, P.K.: On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and Its Applications. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 17(4) (2009)Google Scholar
  15. 15.
    Reyhani-Masoleh, A., Hasan, M.A.: Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2m). IEEE Trans. on Computers 53(8) (2004)Google Scholar
  16. 16.
    Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K.: Robust System Design with Built-In Soft Error Resilience. IEEE Computer 38(2), 43–52 (2005)CrossRefGoogle Scholar
  17. 17.
    Boneh, D., DeMillo, R.A., Lipton, R.J.: On the Importance of Eliminating Errors in Cryptographic Computations. Journal of Cryptology 14, 1–119 (2001)MathSciNetCrossRefGoogle Scholar
  18. 18.
    Song, L., Parhi, K.K.: Low Energy Digit-Serial/Parallel Fnite Feld Multipliers. Journal of VLSI Signal Processing 19(2), 149–166 (1998)CrossRefGoogle Scholar
  19. 19.
    Gaubatz, G., Sunar, B.: Robust Fnite Feld Arithmetic for Fault Tolerant Public-key Cryptography. In: 2nd Workshop on Fault Tolerance and Diagnosis in Cryptography (FTDC), pp. 1–12 (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Vinu K. Narayanan
    • 1
  • Rishad A. Shafik
    • 1
  • Jimson Mathew
    • 1
  • Dhiraj K. Pradhan
    • 1
  1. 1.Department of Computer ScienceUniversity of BristolBristolUK

Personalised recommendations