Isolation Types and Multi-core Architectures

  • Alan Mycroft
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7421)


Programs distributed between two or more cores on a multi-core processor are significantly slowed down when both repeatedly access the same cache line—unless both accesses consist of reads. The hardware performs best when programs satisfy a ‘memory isolation’ property whereby each line of writable memory is available to only one processor at a time. Multi-core memory isolation encapsulates a multiple-reader/single-writer usage, with a cost incurred when changing one writer for another.

This tutorial-style work starts with a historical perspective and then shows how existing work on Kilim and its isolation-type system provides a programming-language form to express such memory isolation including ownership transfer.


Cache Line Memory Hierarchy Message Type Isolation Type Cache Coherency Protocol 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Alan Mycroft
    • 1
  1. 1.Computer LaboratoryUniversity of CambridgeCambridgeUK

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