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\(\textrm{GF}(2^m)\) Finite-Field Multipliers with Reduced Activity Variations

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Book cover Arithmetic of Finite Fields (WAIFI 2012)

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Abstract

Electrical activity variations in a circuit are one of the information leakage used in side channel attacks. In this work, we present \(\textrm{GF}(2^m)\) multipliers with reduced activity variations for asymmetric cryptography. Useful activity of typical multiplication algorithms is evaluated. The results show strong shapes, which can be used as a small source of information leakage. We propose modified multiplication algorithms and multiplier architectures to reduce useful activity variations during an operation.

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References

  1. Bajard, J.-C., Negre, C., Plantard, T.: Subquadratic space complexity binary field multiplier using double polynomial representation. IEEE Transactions on Computers 59(12), 1585–1597 (2010)

    Article  MathSciNet  Google Scholar 

  2. Byrne, A., Meloni, N., Tisserand, A., Popovici, E.M., Marnane, W.P.: Comparison of simple power analysis attack resistant algorithms for an elliptic curve cryptosystem. Journal of Computers 2(10), 52–62 (2007)

    Article  Google Scholar 

  3. Chabrier, T., Pamula, D., Tisserand, A.: Hardware implementation of DBNS recoding for ECC processor. In: Proc. 44th Asilomar Conference on Signals, Systems and Computers, pp. 1129–1133. IEEE (November 2010)

    Google Scholar 

  4. Deschamps, J.-P., Imana, J.L., Sutter, G.D.: Hardware Implementation of Finite-Field Arithmetic. McGraw-Hill (2009)

    Google Scholar 

  5. Erdem, S.S., Yanik, T., Koc, C.K.: Polynomial basis multiplication over GF(2m). Acta Applicandae Mathematicae 93(1-3), 33–55 (2006)

    Article  MathSciNet  MATH  Google Scholar 

  6. Fan, H., Hasan, M.A.: A new approach to subquadratic space complexity parallel multipliers for extended binary fields. IEEE Transactions on Computers 56(2), 224–233 (2007)

    Article  MathSciNet  Google Scholar 

  7. Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic Analysis: Concrete Results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  8. Guo, X., Schaumont, P.: Optimized system-on-chip integration of a programmable ECC coprocessor. ACM Transactions on Reconfigurable Technology and Systems 4(1), 6:1–6:21 (2010)

    Google Scholar 

  9. Hankerson, D., Menezes, A., Vanstone, S.: Guide to Elliptic Curve Cryptography. Springer (2004)

    Google Scholar 

  10. Joye, M.: Defenses Against Side-Channel Analysis. In: Advances in Elliptic Curve Cryptography. London Mathematical Society Lecture Note Series, vol. 317, pp. 87–100. Cambridge University Press (April 2005)

    Google Scholar 

  11. Karatsuba, A., Ofman, Y.: Multiplication of multi-digit numbers on automata. Doklady Akad. Nauk SSSR 145(2), 293–294 (1962) (in Russian); Translation in Soviet Physics-Doklady 44(7), 595–596 (1963)

    Google Scholar 

  12. Koc, C.K., Acar, T.: Montgomery multiplication in GF(2k). Designs, Codes and Cryptography 14(1), 57–69 (1998)

    Article  MathSciNet  MATH  Google Scholar 

  13. Lidl, R., Niederreiter, H.: Introduction to Finite Fields and Their Applications, 2nd edn. Cambridge University Press (1994)

    Google Scholar 

  14. Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer (2007)

    Google Scholar 

  15. Mastrovito, E.: VLSI Architectures for Computation in Galois Fields. PhD thesis, Department of Electrical Engineering, Linkoping University, Sweden (1991)

    Google Scholar 

  16. Montgomery, P.L.: Modular multiplication without trial division. Mathematics of Computation 44(170), 519–521 (1985)

    Article  MathSciNet  MATH  Google Scholar 

  17. Namin, A.H., Huapeng, W., Ahmadi, M.: A high-speed word level finite field multiplier in \(\textrm{F}_{2^m}\) using redundant representation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17(10), 1546–1550 (2009)

    Article  Google Scholar 

  18. Orlando, G., Paar, C.: A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 41–56. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  19. Oswald, E.: Side Channel Analysis. In: Advances in Elliptic Curve Cryptography. London Mathematical Society Lecture Note Series, vol. 317, pp. 69–86. Cambridge University Press (April 2005)

    Google Scholar 

  20. Proakis, J.G., Manolakis, D.G.: Digital Signal Processing. Prentice Hall (1996)

    Google Scholar 

  21. Rodriguez-Henriquez, F., Saqib, N.A., Diaz-Perez, A., Koc, C.K.: Cryptographic Algorithms on Reconfigurable Hardware. Springer (2007)

    Google Scholar 

  22. Savas, E., Koc, C.K.: Finite field arithmetic for cryptography. IEEE Circuits and Systems Magazine 10(2), 40–56 (2010)

    Article  Google Scholar 

  23. Sunar, B.: A generalized method for constructing subquadratic complexity GF(2k) multipliers. IEEE Transactions on Computers 53(9), 1097–1105 (2004)

    Article  MATH  Google Scholar 

  24. Tisserand, A.: Low-power arithmetic operators. In: Piguet, C. (ed.) Low Power Electronics Design, ch. 9. CRC Press (November 2004)

    Google Scholar 

  25. Tisserand, A.: Fast and accurate activity evaluation in multipliers. In: Proc. 42nd Asilomar Conference on Signals, Systems and Computers, pp. 757–761. IEEE (October 2008)

    Google Scholar 

  26. Weste, N.H.E., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edn. Addison Wesley (2004)

    Google Scholar 

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Pamula, D., Tisserand, A. (2012). \(\textrm{GF}(2^m)\) Finite-Field Multipliers with Reduced Activity Variations. In: Özbudak, F., Rodríguez-Henríquez, F. (eds) Arithmetic of Finite Fields. WAIFI 2012. Lecture Notes in Computer Science, vol 7369. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31662-3_11

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  • DOI: https://doi.org/10.1007/978-3-642-31662-3_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-31661-6

  • Online ISBN: 978-3-642-31662-3

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