A New Class of Obstacle Aware Steiner Routing in 3D Integrated Circuits
Three dimensional integration has offered a paradigm shift to the VLSI design industry. It provides increased system integration by either increasing functionality or combining different technologies. Routing phase in 3D ICs plays a critical role during the layout design of 3D ICs. With much more design complexity together with close proximity of the increasing numbers of routing nodes this problem again becomes worse in presence of obstacles across the routing layers. This obstacle aware routing tree construction has become a challenging problem among the researchers recently. In this work, an efficient algorithm has been proposed for the rectilinear minimum Steiner tree (RMST) construction in presence of obstacles across the routing layers using a farthest pair approach. Due to ever increasing design complexity issues, careful measures have been taken to reduce the time complexity of the proposed algorithm. The novelties of this work may be stated as follows (i) proposed algorithm helps to construct an RMST in presence of obstacles, (ii) time complexity of the proposed algorithm is very much competitive with available tools, (iii) proposed algorithm efficiently reduces the number of Steiner points during the construction of RMST in presence of obstacles in comparison to the standard solution available in absence of obstacles. Experimental results are quite encouraging.
KeywordsObstacle aware routing Routing in 3D ICs Farthest pair routing
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