Low Power Design Analysis of PLL Components in Submicron Technology

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)


This paper presents design of 3rd order phase locked loop system for low power applications. The design focuses on reducing power consumption. This design consists of low power phase frequency detector, novel charge pump, fully differential Ring oscillator based VCO, and 2nd order passive loop filter and 7 bit digital frequency divider using 350nm, 180nm and 130nm Technology nodes at 350MHz. Results are carried out on SPICE at various technology nodes. For 3V power supply, power consumption of PLL system is reduced to 37% along with max power of 31mW and min power of 12mW and RMS Value calculated equals to 1.7 V and Average Value is 1.3 V at 350nm technology node.


Phase locked loop Phase frequency detector charge pump loop filter voltage controlled oscillator frequency divider 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Centre for Development of Advanced ComputingMohaliIndia

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