Advertisement

Low Power Design Analysis of PLL Components in Submicron Technology

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)

Abstract

This paper presents design of 3rd order phase locked loop system for low power applications. The design focuses on reducing power consumption. This design consists of low power phase frequency detector, novel charge pump, fully differential Ring oscillator based VCO, and 2nd order passive loop filter and 7 bit digital frequency divider using 350nm, 180nm and 130nm Technology nodes at 350MHz. Results are carried out on SPICE at various technology nodes. For 3V power supply, power consumption of PLL system is reduced to 37% along with max power of 31mW and min power of 12mW and RMS Value calculated equals to 1.7 V and Average Value is 1.3 V at 350nm technology node.

Keywords

Phase locked loop Phase frequency detector charge pump loop filter voltage controlled oscillator frequency divider 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Mann, A.: The Design of a Low-Power Low-Noise Phase Lock Loop. In: IEEE Proceedings of ISQED 2010, pp. 528–531 (April 2010) 5450522Google Scholar
  2. 2.
    Lin, F.: Research and Design of Low Jitter, Wide Locking-Range All-Digital Phase-Locked and Delay-Locked Loops. PhD Thesis, Electrical Engineering (March 2000)Google Scholar
  3. 3.
    Mansuri, M.: Low-Power Low-Jitter On-Chip Clock Generation. PhD Thesis, Electrical Engineering, UCLA (2003)Google Scholar
  4. 4.
    Thakore, K.P.: Low Power and Low Jitter Phase Frequency Detector for Phase Lock Loop. International Journal of Engineering Science and Technology (IJEST) 2(2)Google Scholar
  5. 5.
    Imfeld, K.: Low-Jitter and Low-Power CMOS PLL for Clock Multiplication. In: Solid-State Circuits Conference, ESSCIRC 2006, pp. 174–177 (2006)Google Scholar
  6. 6.
    Shi, X.: Design of Low Phase Noise Low Power CMOS Phase Locked Loops. PhD Thesis, Soutenue LE 20 (November 2008)Google Scholar
  7. 7.
    Ferrando, M.P.: Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04, Texas instrumentation (June 2010)Google Scholar
  8. 8.
    Mustafa, K.: Filtering Techniques: Isolating Analog and Digital Power Supplies in TI’s PLL-Based CDC Devices. Texas Instrumentation (October 2001)Google Scholar
  9. 9.
    Liu, Y.: Power and Jitter Optimized VCO Design Using an On-Chip Supply Noise Monitoring Circuit. IEEE Proceedings, 939–940 (2010) 978-1-4244-7456-1Google Scholar
  10. 10.
    Roche, J.: A Low-Noise Fast-Settling Phase Locked Loop with Loop Bandwidth Enhancement. IEEE Proceedings , pp. 165–168 (2008) 978-1-4244-2332-3Google Scholar
  11. 11.
    Gundel, A.: High Performance Low Phase Noise PLL Clock Synthesizer with LVDS Outputs. In: IEEE Paper Systems, Applications and Technology Conference, LISAT 2006, pp. 1–94 (2006)Google Scholar
  12. 12.
    Wey, T.: A Circuit Technique to Improve Phase-Locked Loop Charge Pump Current Matching. In: IEEE-NEWCAS Conference, pp. 235–238 (June 2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Centre for Development of Advanced ComputingMohaliIndia

Personalised recommendations