Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing

  • Shikha Singh
  • V. Sulochana Verma
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)


With continuous scaling of integrated circuits into deep sub micron process technology, operating at gigahertz frequencies, it has become critical to determine system performance and reliability in interconnects. Scaling of process technology contributes to the greater proximity of adjacent interconnect wires, which leads to an increase in the amount of coupling capacitance between interconnect wires. Also, scaling in device dimensions have not scaled interconnect delays in proportion to gate delays. Thus, interconnect delays account for a major portion of circuit delay. In this paper simultaneous buffer insertion/sizing, wire sizing is done using closed form solution along with designing of Schmitt trigger as a buffer with an operating frequencies of 12-20 GHz so as to minimize crosstalk noise and delay in interconnects. Simulation results using SPICE shows that at 90nm technology node crosstalk noise is reduced by 60% and delay by 56% for 1V power supply.


Crosstalk noise Delay Buffer Insertion Buffer Sizing Wire Sizing 


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  1. 1.
    Hasani, F., Masaoumi, N.: Crosstalk and Delay Optimization Techniques for Nano Scale Interconnects. In: International Conference on Design & Technology of Integrated Systems in Nanoscale Era (2007)Google Scholar
  2. 2.
    Saini, S., Mahesh Kumar, A., Veeramachaneni, S., Srinivas, M.B.: Schmitt Trigger as an alternative to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. In: IEEE Region 10 Conference TENCON (2009)Google Scholar
  3. 3.
    Saini, S., Mahesh Kumar, A., Veeramachaneni, S., Srinivas, M.B.: An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. In: 3rd to 7th International Conference on VLSI Design 2010, Bangalore, pp. 411–416 (January 2010)Google Scholar
  4. 4.
    Saini, S.: A Novel Approach to reduce Delay and Power in VLSI Interconnects, M.S. Thesis Electronics and Communication Engineering (2009)Google Scholar
  5. 5.
    Mezhiba, A., Friedman, E.G.: Frequency Characteristics of High Speed Power Distribution Networks. Analog Integrated Circuits and Signal Processing 35(2/3), 207–214 (2003)CrossRefGoogle Scholar
  6. 6.
    Prasad, V.: Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. In: International Conference on VLSI Design, pp. 417–422. IEEE (2003)Google Scholar
  7. 7.
    Chu, C.C.N., Wong, D.F.: Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing. In: Proceedings of the International Symposium on Physical Design (1997)Google Scholar
  8. 8.
    Kong, J., Koh, C.K.: Simultaneous Driver and Wire Sizing. IEEE Transaction on Very Large Scale Integration (VLSI) Systems (2004)Google Scholar
  9. 9.
    Jiang, I.H.-R.: Crosstalk Driven Interconnect Optimization By Simultaneous Gate And Wire Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(9) (September 2002)Google Scholar
  10. 10.
    National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Centre for Development of Advanced ComputingMohaliIndia

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