Obstacle Aware RMST Generation Using Non-Manhattan Routing for 3D ICs
Successful design and fabrication of three dimensional integrated circuits i.e. 3D ICs have shown a new pathway to the researchers to handle with enormous design complexity of modern day electronic circuits. Moreover, due to the close proximity of logic modules, the interconnect cost has also been reduced in this interconnect centric VLSI design era. In recent years, a group of researchers has also come up with non-manhattan interconnect routing strategies to beat the ever increasing routing cost due to traditional Manhattan routing in 2D planar ICs. Again, in VLSI routing, obstacles are a common and inherent consequence. A routing obstacle is an obstacle that causes a dead end with a large void, or a routing trap. Therefore, to ensure the reliability of routing as well as to ensure complete routability, obstacle avoiding routing tree construction has also become a challenging issue to the modern day researchers. In this work, our approach is in two folds viz. (i) to get the benefit of non-manhattan routing in case of 3D ICs, we have explored the possibilities of using non-manhattan X-routing technique in case of routing in 3D ICs, and (ii) a novel algorithm has been proposed for the construction of Obstacle Aware non-manhattan routing tree construction in 3D VLSI layout design. The experimental results are quite encouraging.
KeywordsNon-manhattan routing Obstacle aware routing Routing in 3D ICs X-routing
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