Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture
Functional units supporting dynamic voltage and frequency scaling are being used today for fine grained power managed digital integrated circuits. The stringent power budget of these low power circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. Experimental results show that the algorithm that operates without any user constraint is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.
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- 3.De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education (1994)Google Scholar
- 4.Katkoori, S., Vemuri, R.: Scheduling for low power under resource and latency constraints. In: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 53–56 (2000)Google Scholar
- 5.Putic, Di Liang, M., Calhoun, B., Lach, J.: Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. In: Proceedings of the IEEE International Conference on Computer Design, pp. 491–497 (October 2009)Google Scholar
- 6.Putic, Di Liang, M., Calhoun, B., Lach, J.: Power switch characterization for fine-grained dynamic voltage scaling. In: Proceedings of the IEEE International Conference on Computer Design, pp. 605–611 (August 2008)Google Scholar
- 7.Bright, M.S., Arslan, T.: Multi-objective design strategy for high- level low power design of DSP systems. In: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 80–83 (May 1999)Google Scholar
- 8.Zhai, B., Blaauw, D., Sylvester, D., Flautner, K.: Theoretical and practical limits of dynamic voltage scaling. In: Proceedings of the IEEE Design Automation Conference, pp. 868–873 (2004)Google Scholar
- 12.Gajski, D., Dutt, N., Wu, A., Lin, S.: High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers (1992)Google Scholar
- 13.Jeon, J., Choi, K., Ahn, Y.: Control Data Flow Graph Toolset, http://dal.snu.ac.kr/?mid=cdfg
- 14.Shiue, W.T., Chakrabarti, C.: ILP-Based Scheme for Low Power Scheduling and Resource Binding. In: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 3, pp. 279–282 (May 2000)Google Scholar
- 15.Blickle, T., Teich, J., Thiele, L.: System Level Synthesis Using Evolutionary Algorithms. In: 5th International Workshop on Hardware/Software Codesign CODES/CASHE, pp. 167–171 (1997)Google Scholar
- 16.Ranganathan, N., Murugavel, A.K.: A low power scheduler using game theory. In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 126–131 (2003)Google Scholar
- 19.Wakabayashi, K., Tanaka, H.: Global scheduling independent of control dependencies based on condition vectors. In: Proceedings of the 29th ACM/IEEE Design Automation Conference, pp. 112–115 (1992)Google Scholar
- 20.Bergamaschi, R.A., Raje, S., Nair, I., Trevillyan, L.: Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. IEEE Transactions on Very Large Scale Integration (VLSI) SystemsGoogle Scholar