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Design of a Novel Reversible Full Adder and Reversible Full Subtractor

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)

Abstract

Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design and nanotechnology based systems. In this paper, we propose an efficient design of a reversible full adder and a reversible full subtractor. In this work, the proposed reversible full adder and reversible full subtractor is better than the existing counterparts in terms of number of reversible gates, and critical path delay. In our design, the full adders are realized using synthesizable, less transistor count and low garbage output PRT-2 gates and the full subtractor is realized using less critical path delay PRT-1 gates. VHDL is used to implement a technology-independent design.

Keywords

Reversible logic design Reversible full adder Reversible full subtractor nanotechnology based systems FPGA 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Pondicherry Engineering CollegePuducherryIndia

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