CMOS 8-Bit Current-Steering Digital Random Return to Zero DAC

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)


Current steering Digital to Analog Converter (DAC) has advantage of high conversion rate and constant output impedance. A digital random return to zero technique to improve dynamic performance is presented in this paper. To demonstrate the proposed technique, 8 bit CMOS DAC is designed and layout is prepared in 90 nm technology. Computation of Integral Non Linearity (INL) and Differential Non Linearity (DNL) performance parameter is done. Chip consumes 57 mW power and 5483 (μm)2 area.


Current steering Digital-to-Analog Converter (DAC) Digital Random Return to Zero (DRRZ) 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Bugeja, A.R., Song, B.-S., Rakers, P.L., Gillig, S.F.: A 14-b, 100-MS/s CMOS DAC designed for spectral performance. IEEE J. Solid-State Circuits 34(12), 1719–1732 (1999)CrossRefGoogle Scholar
  2. 2.
    Chen, T., Gielen, G.G.E.: The analysis and improvement of a current-steering DACs dynamic SFDR-I: The cell-dependent delay differences. IEEE Trans. Circuits Syst. I, Reg. Papers 53(1), 3–15 (2006)CrossRefGoogle Scholar
  3. 3.
    Lin, C.-H., van der Goes, F.M.L., Westra, J.R., Mulder, J., Lin, Y., Arslan, E., Ayranci, E., Liu, X., Bult, K.: A 12 bit 2.9 GS/s DAC with IM3 < -60 dBc beyond 1 GHz in 65 nm CMOS. IEEE J. Solid-State Circuits 44(12), 3285–3293 (2009)CrossRefGoogle Scholar
  4. 4.
    den Bosch, A.V., Steyaert, M., Sansen, W.: SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters. In: Proc. IEEE ICECS, pp. 1193–1196 (September 1999)Google Scholar
  5. 5.
    Luschas, S., Lee, H.-S.: Output impedance requirements for DACs. Proc. IEEE Int. Symp. Circuits Syst. Dig. Tech. Papers, pp. I-861–I-864 (May 2003)Google Scholar
  6. 6.
    Schafferer, B., Adams, R.: A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications. In: Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech, Papers, pp. 360–532 (February 2004)Google Scholar
  7. 7.
    Park, S., Kim, G., Park, S.-C., Kim, W.: A digital-to-analog converter based on differential-quad switching. IEEE J. Solid-State Circuits 37(10), 1335–1338 (2002)CrossRefGoogle Scholar
  8. 8.
    Chan, K.L., Zhu, J., Galton, I.: Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in resolution DACs. IEEE J. Solid-State Circuits 43(9), 2067–2078 (2008)Google Scholar
  9. 9.
    Bugeja, A.R., Song, B.-S.: A self-trimming 14-b 100-MS/s CMOS DAC. IEEE J. Solid-State Circuits 35(12), 1841–1852 (2000)CrossRefGoogle Scholar
  10. 10.
    Huang, Q., Francese, P.A., Martelli, C., Nielsen, J.: A 200 MS/s 14 b 97 mW DAC in 0.18 mum CMOS. In: Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 364–532 (February 2004)Google Scholar
  11. 11.
    Tseng, W.-H., Wu, J.-T., Chu, Y.-C.: A CMOS 8-Bit 1.6 GS/s DAC with Digital Random Return-to-Zero. IEEE Tran. Circuits Syst. II, Exp. Briefs 58(1) (January 2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Department of Electronics and Telecommunication Engineering, Sinhgad College of EngineeringUniversity of PunePuneIndia

Personalised recommendations