A VLSI Architecture for Wavelet Based Image Compression
This paper proposes a VLSI architecture for 2D Haar Wavelet based image compression. The hardware architecture is implemented using Verilog HDL and synthesized using Xilinx ISE software, Xilinx Virtex6 FPGA as target. The architecture is a parallel pipelined hardware structure, which can process 8x8 macro blocks in an image by parallel pipelined fashion. Compared to software and other conventional implementation methods, performance of this architecture is highly efficient in time. This has been implemented onto contemporary FPGA (Xilinx Virtex-6). This is a scalable architecture and can handle any image size. The design has utilized two Block RAMs for processing and 2 Block RAMs for IO storage. The maximum working frequency of the design can be as high as 600MHZ.
KeywordsHaar Wavelet Xilinx Virtex-6 FPGA parallel pipelined architecture processing elements
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