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Design of Efficient Reversible Multiplier

  • H. G. Rangaraju
  • Aakash Babu Suresh
  • K. N. Muralidhara
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 178)

Abstract

Reversible logic is emerging computing paradigm with applications in Ultra-low power Nano computing, quantum computing, Low power CMOS design, Optical Information Processing, Bioinformatics etc. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct NxN reversible multiplier circuit.

Keywords

Reversible Gate Reversible Logic Constant/Garbage Input Garbage Output Quantum Cost Reversible Multiplier 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • H. G. Rangaraju
    • 1
  • Aakash Babu Suresh
    • 2
  • K. N. Muralidhara
    • 3
  1. 1.Department of Electronics and Communication EngineeringGovernment Engineering CollegeChamarajanagarIndia
  2. 2.Robert Bosch Engineering and Business Solutions LimitedBangaloreIndia
  3. 3.Department of Electronics and Communication EngineeringP E S College of EngineeringMandyaIndia

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