A Novel Algorithm for Obstacle Aware RMST Construction during Routing in 3D ICs

Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 177)


Three dimensional integrated circuits offer an attractive alternative to 2D planar ICs by providing increased system integration by either increasing functionality or combining different technologies. Routing phase during layout design of 3D ICs plays a critical role. The problem again becomes worse in presence of obstacles across the routing layers. This obstacle aware routing tree construction has become a challenging problem among the researchers recently. In this work, an efficient algorithm has been proposed for the construction of rectilinear minimum Steiner tree (RMST) in presence of obstacles across the routing layers using a shortest pair approach. Due to ever increasing design complexity issues, careful measures have been taken to reduce the time complexity of the proposed algorithm. The novelties of this work may be stated as follows (i) proposed algorithm helps to construct an RMST in presence of obstacles, (ii) time complexity of the proposed algorithm is very much competitive with available tools, (iii) proposed algorithm efficiently reduces the number of Steiner points during the construction of RMST in presence of obstacles in comparison to the standard solution available in absence of obstacles. Experimental results are quite encouraging.


Obstacle aware routing Routing in 3D ICs Shortest pair routing 


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  1. 1.
    Li, L., Young, E.F.Y.: Obstacle-avoiding Rectilinear Steiner Tree Construction. In: Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 523–528 (2008)Google Scholar
  2. 2.
    Huang, T., Young, E.F.Y.: Obstacle-avoiding Rectilinear Steiner Minimum Tree Construction: An Optimal Approach. In: Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 610–613 (2010)Google Scholar
  3. 3.
    Hu, Y., Feng, Z., Jing, T., Hong, X., Yang, Y., Yu, G., Hu, X., Yan, G.: FORst: A 3-step heuristic for obstacle-avoiding rectilinear Steiner minimum tree construction. Journal of Information & Computational Science 1(3), 107–116 (2004)Google Scholar
  4. 4.
    Liu, J., Zhao, Y., Shragowitz, E., Karypis, G.: A Polynomial Time Approximation Scheme for Rectilinear Steiner Minimum Tree Construction in the Presence of Obstacles. In: 9th International Conference on Electronics, Circuits and Systems, vol. 2, pp. 781–784 (2002)Google Scholar
  5. 5.
    Sapatnekar, S., Goplen, B.: Placement of 3D ICs with thermal and inter-layer via considerations. In: Design Automation Conference, pp. 626–631 (June 2007)Google Scholar
  6. 6.
    Kahng, A.B., Robins, G.: A New Class of Steiner Tree Heuristics with Good Performance: The Iterated 1-Steiner approach. In: International Conference on CAD (1990)Google Scholar
  7. 7.
    Xie, Y., Cong, J., Sapatnekar, S. (eds.): Three-Dimensional Integrated Circuit Design Series: Integrated Circuits and Systems. Springer (2009)Google Scholar
  8. 8.
  9. 9.
    Deng, Y., Maly, W.: Interconnect Characteristics of 2.5d system integration scheme. In: ACM International Symposium on Physical Design, pp. 171–175 (April 2001)Google Scholar
  10. 10.
    Shi, Y., Mesa, P., Yu, H., He, L.: Circuit-Simulated Obstacle-Aware Steiner Routing. ACM Transactions on Design Automation of Electronic Systems 12(3), Article 28 (August 2007)Google Scholar
  11. 11.
    Yan, J.-T., Ming-Ching, Zhi, J., Chen, W.: Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids. In: Asia and South Pacific Design Automation Conference, ASPDAC (2010)Google Scholar

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© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Bengal Engineering and Science UniversityHowrahIndia

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