Advertisement

Area Efficient Architecture for Frequency Domain Multi Channel Digital Down Conversion for Randomly Spaced Signals

  • Latha Sahukar
  • M. Madhavi Latha
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 177)

Abstract

A complete frequency domain processing based digital down conversion architecture is presented in this paper. The conventional complex NCO multiplication is achieved with direct spectrum rotation and various possibilities for frequency domain filtering are discussed. An FFT-IFFT based architecture is implemented in Xilinx Virtex-6 family XC6VLX240T FPGA platform and synthesis is verified. The overlap and add method at the output of IFFT is employed to avoid time domain overlapping. The results demonstrate highly optimized area implementation with respect to conventional DDC architectures. The synthesis results show that the developed core can work upto clock rates of 250 MHz while occupying only 10% of the FPGA slices.

Keywords

Frequency Domain Filtering (FDF) Digital down conversion (DDC) Sample rate conversion non-cooperative communication dynamic decimation 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Han, Y.: A Flexible and Compact Digital Front-End Design for Wideband Software Radio Receivers. In: Science and Technology on Communication Information Security Control Laboratory Zhejiang, China. IEEE (2011)Google Scholar
  2. 2.
    Xu, Y.-J., Wang, H.-Y., Shen, Z.: Modified Polyphase Filter for Arbitrary Sampling Rate Conversion. Huazhong University of Science and Technology Wuhan, China. IEEE (2010)Google Scholar
  3. 3.
    RanTao, Senior Member, IEEE, BingDeng, Zhang, W.: Student Member, IEEE, YueWang: Sampling and Sampling Rate Conversion of Band Limited Signals in the Fractional Fourier Transform Domain. IEEE Transactions on Signal Processing 56(1) (January 2008)Google Scholar
  4. 4.
    Bi, G., Mitra, S.K.: Sampling Rate Conversion in the Frequency Domain [DSP Tips and Tricks]. IEEE Signal Processing Magazine 140 (May 2011)Google Scholar
  5. 5.
    Channelizer cores from RFEL, http://www.rfel.com/channeliser-cores.aspx
  6. 6.
    Signal detection IP core from NSS Communications, http://nsscomm.com/spectrum_search_and_report.html
  7. 7.
    Sample Rate Conversion in Software Configurable Radios, Hentschel, Artech houseGoogle Scholar
  8. 8.
    Lecture notes ECEN4002/5002: Digital Signal ProcessingLab, http://ecee.colorado.edu/~ecen4002/index.html

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Aurora’s Technological and Research Institute (ATRI)HyderabadIndia
  2. 2.ECE Dept.JNTU College of EngineeringHyderabadIndia

Personalised recommendations