Area Efficient Architecture for Frequency Domain Multi Channel Digital Down Conversion for Randomly Spaced Signals

  • Latha Sahukar
  • M. Madhavi Latha
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 177)


A complete frequency domain processing based digital down conversion architecture is presented in this paper. The conventional complex NCO multiplication is achieved with direct spectrum rotation and various possibilities for frequency domain filtering are discussed. An FFT-IFFT based architecture is implemented in Xilinx Virtex-6 family XC6VLX240T FPGA platform and synthesis is verified. The overlap and add method at the output of IFFT is employed to avoid time domain overlapping. The results demonstrate highly optimized area implementation with respect to conventional DDC architectures. The synthesis results show that the developed core can work upto clock rates of 250 MHz while occupying only 10% of the FPGA slices.


Frequency Domain Filtering (FDF) Digital down conversion (DDC) Sample rate conversion non-cooperative communication dynamic decimation 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Aurora’s Technological and Research Institute (ATRI)HyderabadIndia
  2. 2.ECE Dept.JNTU College of EngineeringHyderabadIndia

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