Efficient Techniques for the Implementation of AES SubByte and MixColumn Transformations

  • K. Rahimunnisa
  • M. Priya Zach
  • S. Suresh Kumar
  • J. Jayakumar
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 176)

Abstract

The Advanced Encryption Standard, AES, is commonly used to provide data confidentiality and authentication in several security systems. Designing efficient hardware architecture with small hardware resource usage is a challenge. In this paper, a new technique for the FPGA implementation of the Subbyte and MixColumn transformations, an important part of AES, is introduced. Sub-byte transformation in AES is operated using S-box for each byte. The hardware complexity in AES is dominated by AES substitution box (S-box). S-box is considered as one of the most complicated and costly part of the system due to its non-linear structure. It has high power consumption and high design complexity. In this paper, S-box is optimized by using multiplexer logic design. It is compared to the typical ROM based lookup table and the combinational logic designs. The MixColumn is also optimised by shifting the bytes and reusing the resources. This is also done using the multiplexer logic.

Keywords

AES S-box LUT MixColumn Transformations 

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References

  1. 1.
    National Institute of Standards and Technology (U.S.), Advanced Encryption Standard, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
  2. 2.
    Reddy, S.K., Sakthivel, R., Praneeth, P.: VLSI Implementation of AES Crypto Processor for High Throughput. International Journal of Advanced Engineering Sciences and Technologies 6(1), 022–026 (2011)Google Scholar
  3. 3.
    Xinmiao, Z., Parhi, K.K.: High-speed VLSI architectures for the AES algorithm. IEEE Trans. on VLSI Systems 12, 957–967 (2004)CrossRefGoogle Scholar
  4. 4.
    Ahmad, N., Hasan, R., Jubadi, W.M.: Design of AES S-Box using combinational logic optimization. In: IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), Penang, Malaysia, October 3-5 (2010)Google Scholar
  5. 5.
    Rachh, R.R., Ananda Mohan, P.V.: Implementation of AES S-Boxes using combinational logic. In: IEEE International Symposium on Circuits and Systems, pp. 3294–3297 (2008)Google Scholar
  6. 6.
    Kim, M., Kim, J., Choi, Y.: Low Power Architecture of AES Crypto Module for Wireless Sensor Network. World Academy of Science, Engineering and Technology (2005)Google Scholar
  7. 7.
    Ahmad, E.G., Shaaban, E., Hashem, M.: Lightweight MixColumns Implementation for AES. In: Proceedings of the 9th WSEAS International Conference on Applied Informatics and Communications, pp. 253–258Google Scholar
  8. 8.
    Noo-intara, P., Chantarawong, S., Choomchuay, S.: Architectures for Mix-Column Transform for the AES. In: ICEP (2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • K. Rahimunnisa
    • 1
  • M. Priya Zach
    • 1
  • S. Suresh Kumar
    • 2
  • J. Jayakumar
    • 3
  1. 1.Department of Electronics and Communication EngineeringKarunya UniversityCoimbatoreIndia
  2. 2.Department of Electronics and Communication EngineeringDr. N.G.P Institute of TechnologyCoimbatoreIndia
  3. 3.Department of Electrical and Electronics EngineeringKarunya UniversityCoimbatoreIndia

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