Efficient Techniques for the Implementation of AES SubByte and MixColumn Transformations

  • K. Rahimunnisa
  • M. Priya Zach
  • S. Suresh Kumar
  • J. Jayakumar
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 176)


The Advanced Encryption Standard, AES, is commonly used to provide data confidentiality and authentication in several security systems. Designing efficient hardware architecture with small hardware resource usage is a challenge. In this paper, a new technique for the FPGA implementation of the Subbyte and MixColumn transformations, an important part of AES, is introduced. Sub-byte transformation in AES is operated using S-box for each byte. The hardware complexity in AES is dominated by AES substitution box (S-box). S-box is considered as one of the most complicated and costly part of the system due to its non-linear structure. It has high power consumption and high design complexity. In this paper, S-box is optimized by using multiplexer logic design. It is compared to the typical ROM based lookup table and the combinational logic designs. The MixColumn is also optimised by shifting the bytes and reusing the resources. This is also done using the multiplexer logic.


AES S-box LUT MixColumn Transformations 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • K. Rahimunnisa
    • 1
  • M. Priya Zach
    • 1
  • S. Suresh Kumar
    • 2
  • J. Jayakumar
    • 3
  1. 1.Department of Electronics and Communication EngineeringKarunya UniversityCoimbatoreIndia
  2. 2.Department of Electronics and Communication EngineeringDr. N.G.P Institute of TechnologyCoimbatoreIndia
  3. 3.Department of Electrical and Electronics EngineeringKarunya UniversityCoimbatoreIndia

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