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On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits

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Progress in VLSI Design and Test

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7373))

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Abstract

Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Reversible Computation has high promise oflow power consumption. In this paper, we have proposed a new 4x4 reversible gate (namely BJ gate) which is used to design reversible J-K flip-flop. We have also proposed the design of low power reversible decoders, reversible sequence counter and reversible instruction register. These circuits are analyzed with the existing ones. The comparative results show that the proposed designs of reversible decoders and sequential circuits outperform the existing designs in terms of numbers of gates, garbage outputs and quantum cost. Some lower bounds on the number of gates and garbage outputs of the proposed decoder circuits have also been proposed.

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© 2012 Springer-Verlag Berlin Heidelberg

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Jamal, L., Polash, M.M.A., Mottalib, M.A., Babu, H.M.H. (2012). On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_32

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  • DOI: https://doi.org/10.1007/978-3-642-31494-0_32

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-31493-3

  • Online ISBN: 978-3-642-31494-0

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