A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology

  • Mahendra Sakare
  • Mohit Singh
  • Shalabh Gupta
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7373)


This paper presents a 4 × 20 Gb/s 29-1 pseudo-random binary sequence (PRBS) generator in 90nm CMOS technology to test a 4-bit 20 GS/s digital to analog converter (DAC). The architecture results in generation of four de-correlated sequences from a single 9-bit LFSR (linear feedback shift register) with minimal circuitry. Improved CML (current mode logic) multiplexer design ensures peak-to-peak jitter of 1.7 psec, and negligible amplitude variation. The data latches are clocked at half-rate in order to reduce power dissipation, and are followed by 2:1 multiplexers to achieve the desired data-rate, consuming 51mW per output lane (total 204 mW) of power from a 1 V supply. The PRBS and DAC can together be used for generating pseudo-random multi-level test symbol sequences for high-speed communication links.


Clock Cycle Residual Current Linear Feedback Shift Register Voltage Swing Transition Coverage 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Mahendra Sakare
    • 1
  • Mohit Singh
    • 1
  • Shalabh Gupta
    • 1
  1. 1.Department of Electrical EngineeringIndian Institute of Technology(IIT)-BombayMumbaiIndia

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