Abstract
This paper presents a 4 × 20 Gb/s 29-1 pseudo-random binary sequence (PRBS) generator in 90nm CMOS technology to test a 4-bit 20 GS/s digital to analog converter (DAC). The architecture results in generation of four de-correlated sequences from a single 9-bit LFSR (linear feedback shift register) with minimal circuitry. Improved CML (current mode logic) multiplexer design ensures peak-to-peak jitter of 1.7 psec, and negligible amplitude variation. The data latches are clocked at half-rate in order to reduce power dissipation, and are followed by 2:1 multiplexers to achieve the desired data-rate, consuming 51mW per output lane (total 204 mW) of power from a 1 V supply. The PRBS and DAC can together be used for generating pseudo-random multi-level test symbol sequences for high-speed communication links.
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Singh, M., Sakare, M., Gupta, S.: Testing of high-speed dacs using prbs generation with “alternate-bit-tapping”. In: DATE, pp. 1–6 (2011)
Laskin, E., Voinigescu, S.P.: A 60 mw per lane, 4× 23-gb/s 27-1 prbs generator. IEEE Journal of Solid-State Circuits 41, 2198–2208 (2006)
Kim, J., Kim, J., Jeong, D.: A 20-gb/s full-rate 27-1 prbs generator integrated with 20-ghz pll in 0.13-μm cmos. In: IEEE A-SSCC 2008, pp. 221–224 (2008)
Sham, K., Bommalingaiahnapallya, S., Ahmadi, M., Harjani, R.: A 3×5-gb/s multilane low-power 0.18-μm cmos pseudorandom bit sequence generator. IEEE Transactions on Circuits and Systems II: Express Briefs 55, 432–436 (2008)
Weiss, F., Wohlmuth, H.D., Kehrer, D., Scholtz, A.: A 24-gb/s 27 - 1 pseudo random bit sequence generator ic in 0.13 -μm bulk cmos. In: ESSCIRC, pp. 468–471 (2006)
Heydari, P.: Design and analysis of low-voltage current-mode logic buffers. In: Fourth Inter. Symp. on Quality Electronic Design, pp. 293–298 (2003)
Galal, S., Razavi, B.: 10-gb/s limiting amplifier and laser/modulator driver in 0.18-μm cmos technology. IEEE Journal of Solid-State Circuits 38, 2138–2146 (2003)
Laemmle, B., Sewiolo, B., Weigel, R.: A 29 − 1 up to 25gb/s m-sequence generator ic for uwb radar applications in a low-cost sige bicmos technology. In: German Microwave Conference, pp. 1–4 (2009)
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Sakare, M., Singh, M., Gupta, S. (2012). A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_29
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DOI: https://doi.org/10.1007/978-3-642-31494-0_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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