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Progress in VLSI Design and Test pp 198–208Cite as

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7373))

Abstract

Today’s electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS’89 benchmark circuits.

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Authors and Affiliations

  1. Amrita Vishwa Vidyapeetham, Coimbatore, India

    P. R. Sruthi & M. Nirmala Devi

Authors
  1. P. R. Sruthi
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  2. M. Nirmala Devi
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Editor information

Editors and Affiliations

  1. Department of Information Technology, Bengal Engineering and Science University Shibpur, P.O. Botanic Garden, 711103, Howrah, India

    Hafizur Rahaman

  2. Department of Electronic Science, University of Calcutta, 92, A.P.C. Road, 700009, Kolkata, India

    Sanatan Chattopadhyay

  3. Department of Electronics and Electrical Comm. Engg., Indian Institute of Technology Kharagpur, 721302, West Bengal, India

    Santanu Chattopadhyay

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© 2012 Springer-Verlag Berlin Heidelberg

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Sruthi, P.R., Devi, M.N. (2012). A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_23

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  • DOI: https://doi.org/10.1007/978-3-642-31494-0_23

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-31493-3

  • Online ISBN: 978-3-642-31494-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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