Abstract
Dynamic power estimation is a critical requirement in the design of digital logic for effective design decision. The brute-force way of estimating the power is to apply all the possible input vectors. Since the complexity of modern integrated circuits follow Moore’s trend this technique can no longer be applied for computationally efficient and accurate power estimation. In the literature different techniques are reported for estimating the power either by generating the worst power consuming input vector or by applying some probability based technique.
We have attempted to generate input vectors that result in maximum possible toggling for combinational circuits. In this work, we have modeled combinational circuits using binary integer linear program(BILP) and solved it using the mixed integer linear programming solver CPLEX. Experimental results on ISCAS-85 benchmarks show that the input vectors generated by our methodology result into maximally possible toggling in the circuit for most of the benchmark circuits.
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Tudu, J.T., Malani, D., Singh, V. (2012). ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_20
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DOI: https://doi.org/10.1007/978-3-642-31494-0_20
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