Abstract
Vedic mathematics is the ancient techniques of mathematics, based on 16 simple sutras (formulae). Decimal number system multiplication technique based on such ancient mathematics is reported in this paper. Improvement in speed was achieved through stage reduction by “Nikhilam Navatascaramam Dasatah (NND)” (all from 9 and last from 10) which was adopted from Vedas, during multiplication. Binary coded decimal (BCD) methodology was incorporated with Vedic mathematics, to implement such multiplier for practical VLSI applications. The functionality of these circuits was checked and performance parameters such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. BCD implementation of Vedic multiplier ensures the stage reduction for decimal number, hence substantial reduction in propagation delay compared with earlier reported one, has been investigated. Implementation result offered propagation delay of the resulting (5×5) digit decimal multiplier was only ~5.798ns while the power consumption of the same was ~23.487μW. Almost ~26% improvement in speed from earlier reported decimal multiplier, e.g. parallel implementation methodology, the best architecture reported so far, has been achieved.
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Saha, P., Banerjee, A., Dandapat, A., Bhattacharyya, P. (2012). Design of High Speed Vedic Multiplier for Decimal Number System. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_10
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DOI: https://doi.org/10.1007/978-3-642-31494-0_10
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