Performance Figures of D/A-Converters

  • Martin Clara
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 36)


Static accuracy parameters describe the DC-characteristic of the D/A-converter. In all cases the difference between the actual characteristic and the presumed ideal converter behavior is quantified. The static performance figures are mostly referred to the LSB-size of the converter, in some cases also to the full-scale range. In the following, we assume a D/A-converter with voltage output.


Phase Noise Noise Power Spectral Density Data Converter Noise Transfer Function Sampling Clock 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 5.
    D. Johns, K. Martin, Analog Integrated Circuit Design (Wiley, New York, 1997). ISBN:0-471-14448-7Google Scholar
  2. 20.
    W. Sansen, Analog Design Essentials (Springer, New York, 2006). ISBN:10-387-25746-2Google Scholar
  3. 31.
    R.v.d. Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters (Kluwer Academic Publishers, 1994). ISBN:0-7923-9436-4Google Scholar
  4. 43.
    K. Parthasarathy, R. Geiger, Unambiguous characterization and specification of D/A converter performance, in Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 890–894, 2000Google Scholar
  5. 44.
    R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Wiley, Hoboken, New Jersey, 2004). ISBN:0-471-46585-2Google Scholar
  6. 45.
    B. Boser, B. Wooley, The design of sigma-delta modulation analog-to-digital converters. IEEE J. Solid-State Circ. 23(6), 1298–1308 (1988)CrossRefGoogle Scholar
  7. 46.
    J. Wikner, Studies on CMOS Digital-to-Analog Converters, Ph.D. dissertation, University of Linkping, 2001Google Scholar
  8. 47.
    R. Adams, K.Q. Nguyen, K. Sweetland, A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE J. Solid-State Circ. 33(12), 1871–1878 (1998)CrossRefGoogle Scholar
  9. 48.
    K. Laker, W. Sansen, Design of Analog Integrated Circuits and Systems (McGraw-Hill, New York, 1994). ISBN:00-703-6060-XGoogle Scholar
  10. 49.
    B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, Boston, MA, 2001). ISBN:0-07-118839-8Google Scholar
  11. 50.
    Y. Tsivids, C. McAndrew, Operation and Modeling of the MOS Transistor, 3rd edn. (Oxford University Press, New York, 2011). ISBN:978-0-19-517015-3Google Scholar
  12. 51.
    N. Da Dalt, M. Harteneck, C. Sandner, A. Wiesbauer, Numerical modeling of PLL jitter and the impact of its non-white spectrum on the SNR of sampled signals. Southwest Symposium on Mixed-Signal Design (2001), pp. 38–44Google Scholar
  13. 52.
    M. Shinagawa, Y. Akazawa, T. Wakimoto, Jitter analysis of high-speed sampling systems. IEEE J. Solid-State Circ. 25(1), 220–224 (1990)CrossRefGoogle Scholar
  14. 53.
    N. Da Dalt, M. Harteneck, C. Sandner, A. Wiesbauer, On the Jitter requirements of the sampling clock for analog-to-digital converters. IEEE Trans. Circ. Syst. I. 49(9), 1354–1360 (2002)CrossRefGoogle Scholar
  15. 54.
    A. Hajimiri, T.H. Lee, The Design of Low Noise Oscillators (Kluwer Academic Publisher, 1999). ISBN:0-7923-8455-5Google Scholar
  16. 57.
    A. Mehrotra, Noise analysis of phase-locked loops. IEEE Trans. Circ. Syst. I: Fundamental Theor. Appl. 49(9), 1309–1316 (2002)CrossRefGoogle Scholar
  17. 58.
    L. Hernndez, A. Wiesbauer, S. Paton, A. Di Giandomenico, Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction, in Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 1, pp. I–1072 – I–1075, 2004Google Scholar
  18. 59.
    A. Wiesbauer, M. Clara, M. Harteneck, T. Ptscher, B. Seger, C. Sandner, C. Fleischhacker, A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. IEEE J. Solid-State Circ. 37(7), 866–873 (2002)Google Scholar
  19. 60.
    M. Clara, N. Da Dalt Jitter noise of sampled multitone signals. IEEE Trans. Circ. Syst. II. 58(10), 652–656 (2011)CrossRefGoogle Scholar
  20. 61.
    H. Pan, M. Segami, M. Choi, J. Cao, F. Hattori, A. Abidi, A 3.3V 12b 50-MS/s A/D-converter in 0.6 micron CMOS with over 80-dB SFDR, in Analog Circuit Design - High-Speed Analog-to-Digital Converters, Mixed-Signal Design; PLLs and Synthesizers, ed. by R.v.d. Plassche, J. Huijsing, W. Sansen. (Kluwer Academic Publishers, 2000), pp. 47–73. ISBN:0-7923-7956-XGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Martin Clara
    • 1
  1. 1.LANTIQ-A GmbHVillachAustria

Personalised recommendations