A Unified Processor Model for Compiler Verification and Simulation Using ASM

  • Roland Lezuo
  • Andreas Krall
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7316)

Abstract

For safety critical embedded systems the correctness of the processor, toolchain and compiler is an important issue. Translation validation is one approach for compiler verification. A common semantic framework to represent source and target language is needed and Abstract State Machines (ASMs) are a well suited and established method. In this paper we present a method to show correctness of instruction selection by performing fully automated simulation proofs over symbolic execution traces of state transformations using an automated first-order theorem prover. We applied this approach to an industrial-strength compiler and created the ASM models in such a way that we are able to reuse them to create a cycle-accurate simulator. To achieve fast simulation we compile the ASM models to C++ and present the compilation scheme in this paper. Finally we present our preliminary results which indicate that a unified ASM model is sufficient for proving correct instruction selection and generating efficient cycle-accurate simulators.

Keywords

Single Instruction Multiple Data Intermediate Representation Machine Instruction Very Long Instruction Word Abstract State Machine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Börger, E.: Abstract state machines: A method for high-level system design and analysis (2003)Google Scholar
  2. 2.
    Farahbod, R., Gervasi, V., Glässer, U.: CoreASM: An extensible ASM execution engine. In: Proc. of the 12th International Workshop on Abstract State Machines, pp. 153–165 (2005)Google Scholar
  3. 3.
    Fraser, C.W., Henry, R.R., Proebsting, T.A.: BURG: fast optimal instruction selection and tree parsing. ACM Sigplan Notices 27(4), 68–76 (1992)CrossRefGoogle Scholar
  4. 4.
    Gaul, T.S.: An abstract state macine specification of the DEC-alpha processor family (1995), ftp://www.jair.org/groups/Ealgebras/alpha.pdf
  5. 5.
    Hoder, K., Kovács, L., Voronkov, A.: Interpolation and Symbol Elimination in Vampire. In: Giesl, J., Hähnle, R. (eds.) IJCAR 2010. LNCS, vol. 6173, pp. 188–195. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  6. 6.
    Pnueli, A., Siegel, M., Singerman, F.: Translation validation, pp. 151–166. Springer (1998)Google Scholar
  7. 7.
    Riazanov, A., Voronkov, A.: The design and implementation of VAMPIRE. AI Commun. 15, 91–110 (2002)MATHGoogle Scholar
  8. 8.
    Teich, J., Kutter, P.W., Weper, R.: Description and Simulation of Microprocessor Instruction Sets Using ASMs. In: Gurevich, Y., Kutter, P.W., Vetta, A., Thiele, L. (eds.) ASM 2000. LNCS, vol. 1912, pp. 266–286. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  9. 9.
    Zimmermann, W., Gaul, T.: On the construction of correct compiler back-ends: An ASM approach. Journal of Universal Computer Science 3, 504–567 (1997)MathSciNetMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Roland Lezuo
    • 1
  • Andreas Krall
    • 1
  1. 1.Institute of Computer LanguagesVienna University of TechnologyWienAustria

Personalised recommendations