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Sustainable and Reliable On-Chip Wireless Communication Infrastructure for Massive Multi-core Systems

  • Amlan Ganguly
  • Partha Pande
  • Benjamin Belzer
  • Alireza Nojeh
Part of the Studies in Computational Intelligence book series (SCI, volume 432)

Abstract

The Network-on-Chip paradigm has emerged as an enabling methodology to integrate high number of functional cores on a single die. However, the metal interconnect based multi-hop on-chip networks result in high latency and energy dissipation in data transfer. In order to alleviate these problems several emerging interconnect technologies have been proposed. Wireless NoC architectures are shown to outperform the wired counterparts by several orders of magnitude in energy dissipation while achieving higher data transfer rates. However, reliability of the wireless links along with the metal NoC interconnects are known to be a major concern in the future technology nodes. Powerful error control codes based on product codes can enhance the resilience of the wireless channels making the overall NoC more reliable. A unified error control mechanism to enhance the resilience to transient errors of the wireless links as well as the wireline links is presented. This chapter showcases the achievable performance benefits of the wireless NoC architectures while still maintaining acceptable robustness to transient errors.

Keywords

Wireless Link Product Code Virtual Channel Very Large Scale Inte Voltage Swing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Pavlidis, V.F., Friedman, E.G.: 3-D Topologies for Networks-on-Chip. IEEE Transactions on Very Large Scale Integration (VLSI) 5(10), 1081–1090 (2007)CrossRefGoogle Scholar
  2. 2.
    Shacham, A., et al.: Photonic Network-on-Chip for Future Genera-tions of Chip Multi-Processors. IEEE Transactions on Computers 57(9), 1246–1260 (2008)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Chang, M.F., et al.: CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. In: Proc. of IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 16-20, pp. 191–202 (2008)Google Scholar
  4. 4.
    Zhao, D., Wang, Y.: SD-MAC: Design and Synthesis of A Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip. IEEE Transactions on Computers 57(9), 1230–1245 (2008)CrossRefGoogle Scholar
  5. 5.
    Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1), 70–78 (2002)CrossRefGoogle Scholar
  6. 6.
    Sridhara, S.R., Shanbhag, N.R.: Coding for System-on-Chip Networks: A Unified Framework. IEEE Transactions on Very Large Scale Integration (TVLSI) Systems 13(6), 655–667 (2005)CrossRefGoogle Scholar
  7. 7.
    Ganguly, A., et al.: Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects. IEEE Transactions on VLSI (TVLSI) 17(11), 1626–1639 (2009)CrossRefGoogle Scholar
  8. 8.
    Ganguly, A., et al.: Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems. IEEE Transactions on Computers (TC) 60(10), 1485–1502 (2011)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Ganguly, A., et al.: A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip. In: Proc. of the IEEE Defect and Fault Tolerance Symposium (DFTS), Vancouver, Canada (October 2011)Google Scholar
  10. 10.
    Kumar, A., et al.: Toward Ideal On-Chip Communication Using Express Virtual Channels. IEEE Micro 28(1), 80–90 (2008)CrossRefGoogle Scholar
  11. 11.
    Ogras, U.Y., Marculescu, R.: “It’s a Small World After All”: NoC Performance Optimization Via Long-Range Link Insertion. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14(7), 693–706 (2006)CrossRefGoogle Scholar
  12. 12.
    Chang, M.F., et al.: RF Interconnects for Communications On-Chip. In: Proc. of International Symposium on Physical Design, April 13-16, pp. 78–83 (2008)Google Scholar
  13. 13.
    Kempa, K., et al.: Carbon Nanotubes as Optical Antennae. Advanced Materials 19, 421–426 (2007)CrossRefGoogle Scholar
  14. 14.
    Bertozzi, D., Benini, L., De Micheli, G.: Error control schemes for on-chip communication links: The energy-reliability trade off. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 24(6), 818–831 (2005)CrossRefGoogle Scholar
  15. 15.
    Murali, S., De Micheli, G., Benini, L., Theocharides, T., Vijaykrishnan, N., Irwin, M.: Analysis of error recovery schemes for networks on chips. IEEE Design Test Comput. 22(5), 434–442 (2005)CrossRefGoogle Scholar
  16. 16.
    Rossi, D., Metra, C., Nieuwland, A.K., Katoch, A.: Exploiting ECC redundancy to minimize crosstalk impact. IEEE Design Test Comput. 22(1), 59–70 (2005)CrossRefGoogle Scholar
  17. 17.
    Patel, K.N., Markov, I.L.: Error-correction and crosstalk avoidance in DSM busses. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(10), 1076–1080 (2004)CrossRefGoogle Scholar
  18. 18.
    Rossi, D., Metra, C., Nieuwland, A.K., Katoch, A.: New ECC for crosstalk effect minimization. IEEE Design Test Comput. 22(4), 340–348 (2005)CrossRefGoogle Scholar
  19. 19.
    Fu, B., Ampadu, P.: Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. IET Computers & Digital Techniques 4(3), 251–261 (2010)CrossRefGoogle Scholar
  20. 20.
    Watts, D.J.: Small Worlds: The Dynamics of Networks between Order and Randomness pp. xvi–262. Princeton University Press (1999)Google Scholar
  21. 21.
    Albert, R., Barabasi, A.-L.: Statistical mechanics of complex networks. Reviews of Modern Physics 74, 47–97 (2002)MathSciNetzbMATHCrossRefGoogle Scholar
  22. 22.
    Buchanan, M.: Nexus: Small Worlds and the Groundbreaking Theory of Networks. Norton, W. W. & Company, Inc. (2003)Google Scholar
  23. 23.
    Teuscher, C.: Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs. Chaos 17(2), 26–106 (2007)MathSciNetCrossRefGoogle Scholar
  24. 24.
    Kirkpatrick, S., et al.: Optimization by Simulated Annealing. Science. New Series 220(45978), 671–680Google Scholar
  25. 25.
    Duato, J., et al.: Interconnection Networks - An Engineering Approach. Morgan Kaufmann (2002)Google Scholar
  26. 26.
    Floyd, B.A., et al.: Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters. IEEE Journal of Solid-State Circuits 37(5), 543–552 (2002)CrossRefGoogle Scholar
  27. 27.
    Fukuda, M., et al.: A 0.18 m CMOS Impulse Radio Based UWB Transmitter for Global Wireless Interconnections of 3D Stacked-Chip System. In: Proc. of International Conference Solid State Devices and Materials, pp. 72–73 (September 2006)Google Scholar
  28. 28.
    Hanson, G.W.: On the Applicability of the Surface Imped-ance Integral Equation for Optical and Near Infrared Copper Dipole Antennas. IEEE Transactions on Antennas and Propagation 54(12), 3677–3685 (2006)MathSciNetCrossRefGoogle Scholar
  29. 29.
    Burke, P.J., et al.: Quantitative Theory of Nanowire and Nanotube Antenna Performance. IEEE Transactions on Nanotechnology 5(4), 314–334 (2006)MathSciNetCrossRefGoogle Scholar
  30. 30.
    Huang, Y., et al.: Performance Prediction of Carbon Nano-tube Bundle Dipole Antennas. IEEE Transactions on Nanotechnology 7(3), 331–337 (2008)CrossRefGoogle Scholar
  31. 31.
    Zhou, Y., et al.: Design and Fabrication of Microheaters for Localized Carbon Nanotube Growth. In: Proc. of IEEE Conference on Nanotechnology, pp. 452–455 (2008)Google Scholar
  32. 32.
    Freitag, M., et al.: Hot carrier electroluminescence from a single carbon nanotube. Nano Letters 4(6), 1063–1066 (2004)CrossRefGoogle Scholar
  33. 33.
    Marinis, T.S., et al.: Wafer level vacuum packaging of MEMS sensors. In: Proc. of Electronic Components and Technology Conference, May 31-June 3, vol. 2, pp. 1081–1088 (2005)Google Scholar
  34. 34.
    Lee, B.G., et al.: Ultrahigh-Bandwidth Silicon Photonic Nan-owire Waveguides for On-Chip Networks. IEEE Photonics Technology Letters 20(6), 398–400 (2008)CrossRefGoogle Scholar
  35. 35.
    Green, W.M.J., et al.: Ultra-compact, low RF power, 10Gb/s silicon Mach-Zehnder modulator. Optics Express 15(25), 17106–17113Google Scholar
  36. 36.
    Lu, Z., et al.: Connection-oriented Multicasting in Wormhole-switched Networks on Chip. In: Proc. of IEEE Computer Society Annual Symposium on VLSI, pp. 205–210 (2006)Google Scholar
  37. 37.
    Pande, P.P., et al.: Performance Evaluation and Design Trade-offs for Network-on-chip Interconnect Architectures. IEEE Transactions on Computers 54(8), 1025–1040 (2005)CrossRefGoogle Scholar
  38. 38.
    Ismail, A., Abidi, A.: A 3 to 10GHz LNA Using a Wide-band LC-ladder Matching Network. In: Proc. of IEEE International Solid-State Circuits Conference, February 15-19, pp. 384–534 (2004)Google Scholar
  39. 39.
    Circuits Multi-Projects, http://www.cmp.imag.fr
  40. 40.
    Lojek, B.: Reflectivity of the Silicon Semiconductor Substrate and its Dependence on the Doping Concentration and Intensity of the Irradiation. In: Proc. of the 11th IEEE International Conference on Advanced Thermal Processing of Semiconductors, pp. 215–220 (2003)Google Scholar
  41. 41.
    Hsiao, M.Y.: A class of optimal minimum odd-weight-column SEC-DED codes. IBM J. Res. Dev. 14(4), 395–401 (1970)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Amlan Ganguly
    • 1
  • Partha Pande
    • 2
  • Benjamin Belzer
    • 2
  • Alireza Nojeh
    • 3
  1. 1.Department of Computer EngineeringRochester Institute of TechnologyRochesterUSA
  2. 2.School of Electrical Engineering and Computer ScienceWashington State UniversityPullmanUSA
  3. 3.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada

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