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IFIP International Conference on Autonomous Infrastructure, Management and Security

AIMS 2012: Dependable Networks and Services pp 46–49Cite as

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Hardware Acceleration for Measurements in 100 Gb/s Networks

Hardware Acceleration for Measurements in 100 Gb/s Networks

  • Viktor Puš20 
  • Conference paper
  • 1086 Accesses

Part of the Lecture Notes in Computer Science book series (LNCCN,volume 7279)

Abstract

The paper presents the NetCOPE experimental platform for evaluation of 100 Gb/s networks. The platform consists of acceleration boards with FPGAs, FPGA firmware and control software. While the NetCOPE for 10 Gb/s networks is a mature platform, multiplying the throughput ten times brings major challenges in the platform design.

Keywords

  • FPGA
  • 100 Gb/s
  • hardware acceleration
  • Ethernet
  • PCI Express

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References

  1. COMBO-LXT. CESNET, http://www.liberouter.org/card_combolxt.php

  2. Xilinx Virtex–6 FPGA Family. Xilinx, Inc., http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/index.htm

  3. Brelet, J.-L.: An overview of multiple cam designs in virtex family devices. Xilinx Applixation Note 201, Xilinx Inc. (1999)

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  4. National Research Council Committee on Academic Careers for Experimental Computer Scientists. Academic Careers for Experimental Computer Scientists and Engineers. The National Academies Press (1994)

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  5. Walma, M.: Pipelined cyclic redundancy check (crc) calculation. In: Proceedings of 16th International Conference on Computer Communications and Networks, ICCCN 2007, pp. 365–370 (August 2007)

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Author information

Authors and Affiliations

  1. Association of Legal Entities, CESNET, Zikova 4, 160 00, Prague, Czech Republic

    Viktor Puš

Authors
  1. Viktor Puš
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Editor information

Editors and Affiliations

  1. Faculty of Electrical Engineering, Mathematics, and Computer Science, University of Twente, P.O. Box 217, 7500 AE, Enschede, The Netherlands

    Ramin Sadre

  2. Institute of Computer Science, Masaryk University, Botanická 68a, 602 00, Brno, Czech Republic

    Jiří Novotný & Pavel Čeleda & 

  3. Institut für Informatik (IFI), Universität Zürich, Binzmühlestraße 14, 8050, Zürich, Switzerland

    Martin Waldburger

  4. Institut für Informatik (IFI), Universität Zürich, Binzmühlestrasse 14, 8050, Zürich, Switzerland

    Burkhard Stiller

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© 2012 IFIP International Federation for Information Processing

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Cite this paper

Puš, V. (2012). Hardware Acceleration for Measurements in 100 Gb/s Networks. In: Sadre, R., Novotný, J., Čeleda, P., Waldburger, M., Stiller, B. (eds) Dependable Networks and Services. AIMS 2012. Lecture Notes in Computer Science, vol 7279. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-30633-4_7

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  • .RIS
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  • DOI: https://doi.org/10.1007/978-3-642-30633-4_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-30632-7

  • Online ISBN: 978-3-642-30633-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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