Processor Array Design with the Use of Genetic Algorithm

  • Piotr Ratuszniak
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7116)

Abstract

In this paper a method for processors arrays design dedicated to realization of specimen linear algebra algorithms in FPGA devices is presented. Within an allocation mapping process a genetic algorithm for information dependency graph projection is used and the runtime of the given algorithm is optimized. For larger input matrices, graph decomposition is used which allows the projection results to be obtained. The obtained projection results, with and without graph decomposition, for a specimen linear algebra algorithm are compared. Additionally, a parallel realization of the evolutionary algorithm for multicore processors is presented, which allows projection results to be obtained for larger input matrix sizes.

Keywords

Genetic Algorithm Parallel Architecture Multicore Processor Allocation Mapping FPGA Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Peterson, M.: FPGA Acceleration for outstanding performance. Challenges and Opportunities. In: Parallel Processing and Applied Mathematics, Wroclaw, Poland (2009)Google Scholar
  2. 2.
    Kestur, S., Davis, J., Williams, O.: BLAS Comparision on FPGA, CPU and GPU. In: IEEE Computer Society Symposium on VLSI (2010)Google Scholar
  3. 3.
    Williams, J., George, A.D., Richardson, J., Gosrani, K., Suresh, S.: Computational Density of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration. In: Proc. 4th Reconf. Sys. Inst., Nat’l Center for Supercomp. App., Illinois (2008)Google Scholar
  4. 4.
    Chen, Y.K., Kung, S.Y.: Trend and Challenge on System-on-a-Chip Designs. Journal of Signal Processing Systems 53, 217–229 (2008)CrossRefGoogle Scholar
  5. 5.
    Maslennikow, O.: Podstawy teorii zautomatyzowanego projektowania reprogramowalnych równoległych jednostek przetwarzajacych dla jednoukładowych systemów czasu rzeczywistego. Wyd. Uczelniane Politechniki Koszalińskiej, stron 273 (2004)Google Scholar
  6. 6.
    Ratuszniak, P., Maslennikow, O.: New Conception and Algorithm of Allocation Mapping for Processor Arrays Implemented into Multi-Context FPGA Devices. Mathematica Balkanica 23 (2009)Google Scholar
  7. 7.
    Kung, S.Y.: VLSI Array Processors. Prentice Hall, Englewood Cliffs (1988)Google Scholar
  8. 8.
    Quinton, P., Robert, Y.: Systolic algorithms and architectures. Prentice Hall (1991)Google Scholar
  9. 9.
    Sergyienko, A., Kaniewski, J., Maslennikow, O., Wyrzykowski, R.: A metod for mapping DSP algorithm into application specific processor. In: Proc. 24th Euromicro Conference on Parallel and Distributed Processing, vol. 1. IEEE Comp. Soc. Press, Vasteras (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Piotr Ratuszniak
    • 1
  1. 1.Koszalin University of TechnologyKoszalinPoland

Personalised recommendations