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European Conference on Parallel Processing

Euro-Par 2011: Euro-Par 2011: Parallel Processing Workshops pp 315–323Cite as

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Enabling Next-Generation Parallel Circuit Simulation with Trilinos

Enabling Next-Generation Parallel Circuit Simulation with Trilinos

  • Chris Baker30,
  • Erik Boman31,
  • Mike Heroux31,
  • Eric Keiter31,
  • Siva Rajamanickam31,
  • Rich Schiek31 &
  • …
  • Heidi Thornquist31 
  • Conference paper
  • 1389 Accesses

  • 2 Citations

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 7155)

Abstract

The Xyce Parallel Circuit Simulator, which has demonstrated scalable circuit simulation on hundreds of processors, heavily leverages the high-performance scientific libraries provided by Trilinos. With the move towards multi-core CPUs and GPU technology, retaining this scalability on future parallel architectures will be a challenge. This paper will discuss how Trilinos is an enabling technology that will optimize the trade-off between effort and impact for application codes, like Xyce, in their transition to becoming next-generation simulation tools.

Keywords

  • circuit simulation
  • parallel computing
  • hybrid computing
  • preconditioned iterative methods
  • load balancing

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Author information

Authors and Affiliations

  1. Oak Ridge National Laboratory, Oak Ridge, TN, 37831, USA

    Chris Baker

  2. Sandia National Laboratories, Albuquerque, NM, 87185, USA

    Erik Boman, Mike Heroux, Eric Keiter, Siva Rajamanickam, Rich Schiek & Heidi Thornquist

Authors
  1. Chris Baker
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  2. Erik Boman
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  3. Mike Heroux
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  4. Eric Keiter
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  5. Siva Rajamanickam
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  6. Rich Schiek
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  7. Heidi Thornquist
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Editor information

Editors and Affiliations

  1. Scilytics, Koellnerhofgasse 3/15A, 1010, Vienna, Austria

    Michael Alexander

  2. ICAR-CNR, Via P. Castellino, 111, 80131, Napoli, Italy

    Pasqua D’Ambra

  3. University of Amsterdam, 1090, Amsterdam, Netherlands

    Adam Belloum

  4. Innovative Computing Laboratory, The University of Tennessee, USA

    George Bosilca

  5. Department of Experimental Medicine and Clinic, University Magna Græcia, 88100, Catanzaro, Italy

    Mario Cannataro

  6. Computer Science Department, University of Pisa, Italy

    Marco Danelutto

  7. Second University of Naples, Italy

    Beniamino Di Martino

  8. TU München, Boltzmannstr. 3, 85748, Garching, Germany

    Michael Gerndt

  9. Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Emmanuel Jeannot & Raymond Namyst & 

  10. Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Jean Roman

  11. Oak Ridge National Laboratory, Computer Science and Mathematics Division, 37831-6164, Oak Ridge, TN, USA

    Stephen L. Scott

  12. Department of Scientific Computing, University of Vienna, Nordbergstr. 15/3C, 1090, Vienna, Austrial

    Jesper Larsson Traff

  13. Computer Science and Mathematics Division, Oak Ridge National Laboratory, 37831, Oak Ridge, TN, USA

    Geoffroy Vallée

  14. Technische Universität München, Germany

    Josef Weidendorfer

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© 2012 Springer-Verlag Berlin Heidelberg

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Cite this paper

Baker, C. et al. (2012). Enabling Next-Generation Parallel Circuit Simulation with Trilinos. In: Alexander, M., et al. Euro-Par 2011: Parallel Processing Workshops. Euro-Par 2011. Lecture Notes in Computer Science, vol 7155. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29737-3_36

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  • DOI: https://doi.org/10.1007/978-3-642-29737-3_36

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-29736-6

  • Online ISBN: 978-3-642-29737-3

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