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European Conference on Parallel Processing

Euro-Par 2011: Euro-Par 2011: Parallel Processing Workshops pp 281–291Cite as

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A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors

A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors

  • Thomas Canhao Xu30,31,
  • Pasi Liljeberg30,31 &
  • Hannu Tenhunen30,31 
  • Conference paper
  • 1337 Accesses

  • 1 Citations

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 7155)

Abstract

In this paper, we propose a greedy heuristic approximation scheduling algorithm for future multicore processors. It is expected that hundreds of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). To reduce on-chip communication delay, 3D integration with Through Silicon Vias (TSVs) is introduced to replace the 2D counterpart. Multiple functional layers can be stacked in a 3D CMP. However, operating system process scheduling, one of the most important design issues for CMP systems, has not been well addressed for such a system. We define a model for future 3D CMPs, based on which a scheduling algorithm is proposed to reduce cache access latencies and the delay of inter process communications (IPC). We explore different scheduling possibilities and discuss the advantages and disadvantages of our algorithm. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under two workloads, the execution times of our scheduling in two configurations (2 and 4 threads) are reduced by 15.58% and 8.13% respectively, compared with the other schedulings. Our study provides a guideline for designing scheduling algorithms for 3D multicore processors.

Keywords

  • Schedule Algorithm
  • Multicore Processor
  • Core Allocation
  • Inter Process Communication
  • Shared Cache

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This work is supported by Academy of Finland and Nokia Foundation.

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References

  1. Dally, W.J., Towles, B.: Route packets, not wires: on-chip inteconnection networks. In: Proceedings of the 38th Conference on Design Automation, pp. 684–689 (June 2001)

    Google Scholar 

  2. Intel: Intel research areas on microarchitecture (May 2011), http://techresearch.intel.com/projecthome.aspx?ResearchAreaId=11

  3. Sylvester, D., Keutzer, K.: Getting to the bottom of deep submicron. In: ICCAD 1998, pp. 203–211 (November 1998)

    Google Scholar 

  4. Velenis, D., Stucchi, M., Marinissen, E., Swinnen, B., Beyne, E.: Impact of 3d design choices on manufacturing cost. In: IEEE 3DIC 2009, pp. 1–5 (September 2009)

    Google Scholar 

  5. Xu, T.C., Liljeberg, P., Tenhunen, H.: Optimal number and placement of through silicon vias in 3d network-on-chip. In: Proc. of the 14th DDECS. IEEE (2011)

    Google Scholar 

  6. Leutenegger, S.T., Vernon, M.K.: The performance of multiprogrammed multiprocessor scheduling algorithms. In: Proc. of the SIGMETRICS, pp. 226–236 (April 1990)

    Google Scholar 

  7. Chen, C., Lee, C., Hou, E.: Efficient scheduling algorithms for robot inverse dynamics computation on a multiprocessor system. IEEE Transactions on Systems, Man and Cybernetics 18(5), 729–743 (1988)

    CrossRef  Google Scholar 

  8. Hakem, M., Butelle, F.: Dynamic critical path scheduling parallel programs onto multiprocessors. In: Proceedings of 19th IEEE IPDPS, p. 203b (April 2005)

    Google Scholar 

  9. Sharma, D.D., Pradhan, D.K.: Processor allocation in hypercube multicomputers: Fast and efficient strategies for cubic and noncubic allocation. IEEE Transactions on Parallel and Distributed Systems 6(10), 1108–1123 (1995)

    CrossRef  Google Scholar 

  10. Laudon, J., Lenoski, D.: The sgi origin: a ccnuma highly scalable server. In: Proc. of the 24th International Symposium on Computer Architecture, pp. 241–251 (June 1997)

    Google Scholar 

  11. Chen, Y.J., Yang, C.L., Chang, Y.S.: An architectural co-synthesis algorithm for energy-aware network-on-chip design. J. Syst. Archit. 55(5-6), 299–309 (2009)

    CrossRef  Google Scholar 

  12. Hu, J., Marculescu, R.: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: DATE 2004, p. 10234. IEEE Computer Society, Washington, DC (2004)

    Google Scholar 

  13. IBM: Ibm power 7 processor. In: Hot Chips 2009 (August 2009)

    Google Scholar 

  14. Shyamkumar, T., Naveen, M., Ho, A.J., Jouppi Norman, P.: Cacti 5.1. Technical Report HPL-2008-20, HP Labs (2008)

    Google Scholar 

  15. Semiconductor Industry Association: The international technology roadmap for semiconductors (itrs) (2007), http://www.itrs.net/Links/2007ITRS/Home2007.htm

  16. Lau, J.H.: Tsv manufacturing yield and hidden costs for 3d ic integration. In: Proc. of the 60th ECTC, pp. 1031 –1042 (June 2010)

    Google Scholar 

  17. Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: DSD, pp. 180–187 (September 2003)

    Google Scholar 

  18. Magnusson, P., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)

    CrossRef  Google Scholar 

  19. Bailey, D.H.: Ffts in external or hierarchical memory. The Journal of Supercomputing 4, 23–35 (1990), doi:10.1007/BF00162341

    CrossRef  Google Scholar 

  20. Blelloch, G.E., Leiserson, C.E., Maggs, B.M., Plaxton, C.G., Smith, S.J., Zagha, M.: A comparison of sorting algorithms for the connection machine cm-2. In: Proceedings of the 3rd SPAA, pp. 3–16. ACM, New York (1991)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Turku Center for Computer Science, Joukahaisenkatu 3-5 B, 20520, Turku, Finland

    Thomas Canhao Xu, Pasi Liljeberg & Hannu Tenhunen

  2. Department of Information Technology, University of Turku, 20014, Turku, Finland

    Thomas Canhao Xu, Pasi Liljeberg & Hannu Tenhunen

Authors
  1. Thomas Canhao Xu
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  2. Pasi Liljeberg
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  3. Hannu Tenhunen
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Editor information

Editors and Affiliations

  1. Scilytics, Koellnerhofgasse 3/15A, 1010, Vienna, Austria

    Michael Alexander

  2. ICAR-CNR, Via P. Castellino, 111, 80131, Napoli, Italy

    Pasqua D’Ambra

  3. University of Amsterdam, 1090, Amsterdam, Netherlands

    Adam Belloum

  4. Innovative Computing Laboratory, The University of Tennessee, USA

    George Bosilca

  5. Department of Experimental Medicine and Clinic, University Magna Græcia, 88100, Catanzaro, Italy

    Mario Cannataro

  6. Computer Science Department, University of Pisa, Italy

    Marco Danelutto

  7. Second University of Naples, Italy

    Beniamino Di Martino

  8. TU München, Boltzmannstr. 3, 85748, Garching, Germany

    Michael Gerndt

  9. Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Emmanuel Jeannot & Raymond Namyst & 

  10. Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Jean Roman

  11. Oak Ridge National Laboratory, Computer Science and Mathematics Division, 37831-6164, Oak Ridge, TN, USA

    Stephen L. Scott

  12. Department of Scientific Computing, University of Vienna, Nordbergstr. 15/3C, 1090, Vienna, Austrial

    Jesper Larsson Traff

  13. Computer Science and Mathematics Division, Oak Ridge National Laboratory, 37831, Oak Ridge, TN, USA

    Geoffroy Vallée

  14. Technische Universität München, Germany

    Josef Weidendorfer

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© 2012 Springer-Verlag Berlin Heidelberg

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Xu, T.C., Liljeberg, P., Tenhunen, H. (2012). A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors. In: Alexander, M., et al. Euro-Par 2011: Parallel Processing Workshops. Euro-Par 2011. Lecture Notes in Computer Science, vol 7155. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29737-3_32

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  • DOI: https://doi.org/10.1007/978-3-642-29737-3_32

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  • Print ISBN: 978-3-642-29736-6

  • Online ISBN: 978-3-642-29737-3

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