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European Conference on Parallel Processing

Euro-Par 2011: Euro-Par 2011: Parallel Processing Workshops pp 245–247Cite as

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HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip

HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip

  • Martti Forsell30 &
  • Jesper Larsson Träff31 
  • Conference paper
  • 1328 Accesses

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 7155)

Abstract

Despite the processor industry having more or less successfully invested already 10 years to develop better and increasingly parallel multicore architectures, both software community and educational institutions appear still to rely on the sequential computing paradigm as the primary mechanism for expressing the (very often originally inherently parallel) functionality, especially in the arena of general purpose computing. In that respect, parallel programming has remained a hobby of highly educated specialists and is still too often being considered as too difficult for the average programmer. Excuses are various: lack of education, lack of suitable easy-to-use tools, too architecture-dependent mechanisms, huge existing base of sequential legacy code, steep learning curves, and inefficient architectures. It is important for the scientific community to analyze the situation and understand whether the problem is with hardware architectures, software development tools and practices, or both. Although we would be tempted to answer this question (and actually try to do so elsewhere), there is strong need for wider academic discussion on these topics and presentation of research results in scientific workshops and conferences.

Keywords

  • Hardware Architecture
  • Steep Learning Curve
  • Average Programmer
  • Software Community
  • Parallel Programming Model

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Author information

Authors and Affiliations

  1. VTT, Technical Research Centre of Finland, Oulu, Finland

    Martti Forsell

  2. Faculty of Computer Science, Department of Scientific Computing, University of Vienna, Vienna, Austria

    Jesper Larsson Träff

Authors
  1. Martti Forsell
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  2. Jesper Larsson Träff
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Editor information

Editors and Affiliations

  1. Scilytics, Koellnerhofgasse 3/15A, 1010, Vienna, Austria

    Michael Alexander

  2. ICAR-CNR, Via P. Castellino, 111, 80131, Napoli, Italy

    Pasqua D’Ambra

  3. University of Amsterdam, 1090, Amsterdam, Netherlands

    Adam Belloum

  4. Innovative Computing Laboratory, The University of Tennessee, USA

    George Bosilca

  5. Department of Experimental Medicine and Clinic, University Magna Græcia, 88100, Catanzaro, Italy

    Mario Cannataro

  6. Computer Science Department, University of Pisa, Italy

    Marco Danelutto

  7. Second University of Naples, Italy

    Beniamino Di Martino

  8. TU München, Boltzmannstr. 3, 85748, Garching, Germany

    Michael Gerndt

  9. Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Emmanuel Jeannot & Raymond Namyst & 

  10. Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France

    Jean Roman

  11. Oak Ridge National Laboratory, Computer Science and Mathematics Division, 37831-6164, Oak Ridge, TN, USA

    Stephen L. Scott

  12. Department of Scientific Computing, University of Vienna, Nordbergstr. 15/3C, 1090, Vienna, Austrial

    Jesper Larsson Traff

  13. Computer Science and Mathematics Division, Oak Ridge National Laboratory, 37831, Oak Ridge, TN, USA

    Geoffroy Vallée

  14. Technische Universität München, Germany

    Josef Weidendorfer

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© 2012 Springer-Verlag Berlin Heidelberg

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Cite this paper

Forsell, M., Träff, J.L. (2012). HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip. In: Alexander, M., et al. Euro-Par 2011: Parallel Processing Workshops. Euro-Par 2011. Lecture Notes in Computer Science, vol 7155. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29737-3_28

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  • DOI: https://doi.org/10.1007/978-3-642-29737-3_28

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-29736-6

  • Online ISBN: 978-3-642-29737-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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