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A Reversible Processor Architecture and Its Reversible Logic Design

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Reversible Computation (RC 2011)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 7165))

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Abstract

We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.

All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.

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Thomsen, M.K., Axelsen, H.B., Glück, R. (2012). A Reversible Processor Architecture and Its Reversible Logic Design. In: De Vos, A., Wille, R. (eds) Reversible Computation. RC 2011. Lecture Notes in Computer Science, vol 7165. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29517-1_3

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  • DOI: https://doi.org/10.1007/978-3-642-29517-1_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-29516-4

  • Online ISBN: 978-3-642-29517-1

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