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A Reversible Processor Architecture and Its Reversible Logic Design

  • Michael Kirkedal Thomsen
  • Holger Bock Axelsen
  • Robert Glück
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7165)

Abstract

We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.

All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.

Keywords

Program Counter Memory Instruction Gate Count Branch Register Address Calculation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Michael Kirkedal Thomsen
    • 1
  • Holger Bock Axelsen
    • 1
  • Robert Glück
    • 1
  1. 1.DIKU, Department of Computer ScienceUniversity of CopenhagenCopenhagenDenmark

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