Refinement-Based Modeling of 3D NoCs

  • Maryam Kamali
  • Luigia Petre
  • Kaisa Sere
  • Masoud Daneshtalab
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7141)


Three-dimensional Networks-on-Chip (3D NoC) have recently emerged essentially via the stacking of multiple layers of two-dimensional NoCs. The resulting structures can support a very high level of parallelism for both communication and computation as well as higher speeds, at the cost of increased complexity. To address the potential problems due to the highly complex NoCs, we study them with formal methods. In particular, we base our study on the refinement relation between models of the same system. We propose three abstract models of 3D NoCs, M 0, M 1, and M 2 so that \(M_0 \sqsubseteq M_1 \sqsubseteq M_2\), where ‘\(\sqsubseteq\)’ denotes the refinement relation. Each of these models provides templates for communication constraints and guarantees the communication correctness. We then show how to employ one of these models for reasoning about the communication correctness of the XYZ-routing algorithm.


Abstract Model Static Part Switching Event Dynamic Part Proof Obligation 
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  1. 1.
    Abrial, J.R.: A System Development Process with Event-B and the Rodin Platform. In: Butler, M., Hinchey, M.G., Larrondo-Petrie, M.M. (eds.) ICFEM 2007. LNCS, vol. 4789, pp. 1–3. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  2. 2.
    Abrial, J.R.: Modeling in Event-B: System and Software Design. Cambridge University Press (2010)Google Scholar
  3. 3.
    Abrial, J.R.: The B-Book: Assigning Programs to Meanings. Cambridge University Press (1996)Google Scholar
  4. 4.
    Abrial, J.R., Cansell, D., Mery, D.: Refinement and Reachability in Even-B. In: 4th International Conference of B and Z Users, pp. 129–148 (2005)Google Scholar
  5. 5.
    Abrial, J.R., Hallerstede, S.: Refinement, Decomposition and Instantiation of Discrete Models: Application to Event-B. In: Fundamenta Informaticae, pp. 1–28 (2007)Google Scholar
  6. 6.
    Andreasson, D., Kumar, S.: Slack-Time Aware-Routing in NoC Systems. In: IEEE International Symposium on Circuits and Systems, pp. 2353–2356. IEEE (2005)Google Scholar
  7. 7.
    Arditi, L., Berry, G., Kishinevsky, M.: Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol. 3312, pp. 128–143. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  8. 8.
    Back, R.J., Sere, K.: Stepwise Refinement of Action Systems. In: van de Snepscheut, J.L.A. (ed.) MPC 1989. LNCS, vol. 375, pp. 115–138. Springer, Heidelberg (1989)CrossRefGoogle Scholar
  9. 9.
    Back, R.J., Sere, K.: Superposition Refinement of Reactive Systems. Formal Aspects of Computing 8(3), 324–346 (1996)zbMATHCrossRefGoogle Scholar
  10. 10.
    Borrione, D., Helmy, A., Pierre, L., Schmaltz, J.: A Formal Approach to the Verification of Networks on Chip. EURASIP Journal on Embedded Systems 2009(1), 1–14 (2009)CrossRefGoogle Scholar
  11. 11.
    Duan, X., Zhang, D., Sun, X.: A Condition of Deadlock-free Routing in Mesh Network. In: Second International Conference on Intelligent Networks and Intelligent Systems, pp. 242–245 (2009)Google Scholar
  12. 12.
    Ebrahimi, M., Daneshtalab, M., Liljeberg, P., Tenhunen, H.: HAMUM A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs. In: The 18th Euromicro Conference on Parallel, Distributed and Network-Based Computing (2010)Google Scholar
  13. 13.
    Feero, B.S., Pande, P.: Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. IEEE Transactions on Computers, 32–45 (2009)Google Scholar
  14. 14.
    Grecu, C., et al.: A Scalable Communication-Centric SoC Interconnect Architecture. In: 5th International Symposiom Quality Electronic Design (ISQED 2004), pp. 343–348 (2004)Google Scholar
  15. 15.
    Gupta, R., Guernic, P.L., Skuhla, S.K.: Formal methods and models for system design: a system level perspective. Kluwer Academic Publishers (2004)Google Scholar
  16. 16.
    Harrison, J.: Formal Verification at Intel. In: Symposium on Logic in Computer Science (2003)Google Scholar
  17. 17.
    Jerger, N.E., Peh, L.S., Lipasti, M.H.: Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. In: International Conference Computer Architecture, China, pp. 229–240 (2008)Google Scholar
  18. 18.
    Katz, S.: A Superimposition Control Construct for Distributed Systems. ACM Transactions on Programming Languages and Systems, 337–356 (1993)Google Scholar
  19. 19.
    Kaivola, R., Ghughal, R., Narasimhan, N., Telfer, A., Whittemore, J., Pandav, S., Slobodová, A., Taylor, C., Frolov, V., Reeber, E., Naik, A.: Replacing Testing with Formal Verification in Intel® CoreTM i7 Processor Execution Engine Validation. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 414–429. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  20. 20.
    Kim, Y.B., Kim, Y.-B.: Fault-Tolerant Source Routing for Networks-on-Chip. In: 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 12–20. IEEE Computer Society (2007)Google Scholar
  21. 21.
    Liao, W., Hsiung, P.: Creating a Formal Verification Platform for IBM CoreConnect-based SoC. In: The 1st International Workshop on Automasted Technology for Verificatin and Analysis (ATVA 2003), pp. 7–18 (2003)Google Scholar
  22. 22.
    Loi, I., Benini, L.: An Efficient Distributed Memory Interface for Many-Core Platform with 3D Stacked DRAM. In: Proc. of the DATE Conference, Germany, pp. 99–104 (2010)Google Scholar
  23. 23.
    Lu, Z., Yin, B., Jantsch, A.: Connection-Oriented Multicasting in Wormhole-Switched Networks on Chip. In: Emerging VLSI Technologies and Architectures, pp. 205–211 (2006)Google Scholar
  24. 24.
    Montaana, J.M., Koibuchi, M., Matsutani, H., Amano, H.: Balanced Dimension-Order Routing for k-ary n-cubes. In: International Conference on Parallel Processing (2009)Google Scholar
  25. 25.
    Nayebi, A., Meraji, S., Shamaei, A., Sarbazi-azad, H.: XMulator: A listener-Based Integrated Simulation Platform for Interconnection Networks. In: Asia International Conference on Modeling and Simulation, pp. 128–132 (2007)Google Scholar
  26. 26.
    Palesi, M., Holsmark, R., Kumar, S., Catania, V.: Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, 316–330 (2009)Google Scholar
  27. 27.
    Park, D., et al.: Mira, A Multi-Layered On-Chip Interconnect Router Architecture. In: ISCA 2008, pp. 251–261 (2008)Google Scholar
  28. 28.
    Tsiopoulos, L., Walden, M.: Formal Development of NoC Systems in B. Nordic Journal of Computing, 127–145 (2006)Google Scholar
  29. 29.
    Yan, S., Lin, B.: Design of Application-Specific 3D Networks-on-Chip Architectures. In: IEEE International Conference on Computer Design (ICCD 2008), pp. 142–149 (2008)Google Scholar
  30. 30.
  31. 31.

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Maryam Kamali
    • 1
    • 2
  • Luigia Petre
    • 1
  • Kaisa Sere
    • 1
  • Masoud Daneshtalab
    • 3
  1. 1.Åbo Akademi UniversityFinland
  2. 2.Turku Centre for Computer Science (TUCS)Finland
  3. 3.University of TurkuFinland

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