Abstract
This paper describes reconfigurable two’s complement multiplier using Baugh Wooley’s algorithm supporting six modes of operation. A fixed width Baugh Wooley multiplier is used as prototype for the architecture. Error reduction technique based on bias compensation vector is introduced in the design to achieve a low error fixed width product. Clock gating technique and zero input method is used to obtain a power efficient design. A power reduction of 8.14% and 7.39% is achieved for the current design compared to other non-reconfigurable and reconfigurable techniques. Also a higher clock frequency of 200 MHz is supported by the current architecture compared to other reconfigurable structure which supports 100 MHz for the same reconfigurable two’s complement multiplication. Area of the proposed power efficient architecture is also reduced by 32.64% compared to the previous reconfigurable architecture.
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Sakthivel, R., Vanitha, M., Kittur, H.M. (2012). Low-Power Area Efficient Reconfigurable Pipelined Two’s Complement Multiplier with Reduced Error. In: Krishna, P.V., Babu, M.R., Ariwa, E. (eds) Global Trends in Computing and Communication Systems. ObCom 2011. Communications in Computer and Information Science, vol 269. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29219-4_36
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DOI: https://doi.org/10.1007/978-3-642-29219-4_36
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