A Dual-Grained FTL for Flash Memory

  • Junjie Wang
  • Lihua Yue
  • Peiquan Jin
  • Rui Wang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7240)


Flash memory has been widely used in both embedded devices and enterprise storage devices, due to its specific characteristics such as small size, light weight, high speed, shock resistance, and less energy consumption. However, in order to deal with the special limitation of flash memory, i.e., erase-before-write, an intermediate software layer called flash translation layer (FTL) was employed in modern flash-based disks to map logical page addresses from the file system to physical page addresses used in flash memory. However, most existing FTL schemes suffer from the overhead of small random writes and merge operations, especially full merges. In this paper, we proposed a novel FTL named DGFTL (Dual-Grained FTL), which divides flash memory into two regions, namely a page region and a block region. DGFTL uses new algorithms to manage the dual-grained flash memory and can effectively transfer small random writes into sequential ones. This leads to more efficient switch merges and less costly full merges and partial merges. Our experimental results show that DGFTL reduces the count of erase operation by more than 50% over some existing flash memory management techniques.


Data Block Flash Memory Block Region Solid State Drive NAND Flash 
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  1. 1.
    Wikipedia: Flash memory (2010),
  2. 2.
    Intel Corporation: Understanding the Flash Translation Layer (FTL) Specification. Technical report (1992)Google Scholar
  3. 3.
    Kim, J., Kim, J.M., Noh, S.H., et al.: A Space-efficient Flash Translation Layer for Compact Flash Systems. IEEE Transactions on Consumer Electronics 48(2), 366–375 (2002)CrossRefGoogle Scholar
  4. 4.
    Lee, S.-W., Park, D.-J., Chung, T.-S., et al.: A Log Buffer Based Flash Translation Layer using Fully Associative Sector Translation. ACM Transactions on Embedded Computing Systems 6(3), article 18 (2007)Google Scholar
  5. 5.
    Kang, J.-U., Jo, H., Kim, J.-S., et al.: A Superblock-based Flash Translation Layer for NAND Flash Memory. In: EMSOFT 2006 (2006)Google Scholar
  6. 6.
    Park, C., Cheon, W., Kang, J., et al.: A Reconfigurable FTL (Flash Translation Layer) Architecture for NAND Flash-Based Applications. ACM Transactions on Embedded Computing Systems 7(4), article 38 (2008)Google Scholar
  7. 7.
    Lee, S., Shin, D., Kim, Y.-J., et al.: LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems. ACM SIGOPS Operating Systems Review 42(6), 36–42 (2008)CrossRefGoogle Scholar
  8. 8.
    Kang, S., Park, S., Jung, H., et al.: Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices. IEEE Trans. Computers 58(6), 744–758 (2009)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Jin, P.Q., Su, X., Li, Z., et al.: A Flexible Simulation Environment for Flash-aware Algorithms. In: Proc. of CIKM 2009, demo. ACM Press (2009)Google Scholar
  10. 10.
    Lee, S.-W., Moon, B.: Design of Flash-Based DBMS: An In-Page Logging Approach. In: SIGMOD 2007, Beijing, China (June 2007)Google Scholar
  11. 11.
    Bucy, J.S., Schindler, J., Schlosser, S.W., et al.: The DiskSim Simulation Environment Version 4.0 Reference Manual. Carnegie Mellon University Technical Report (2008)Google Scholar
  12. 12.
    Kim, H., Ahn, S.: BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In: Proc. Sixth USENIX Conf. File and Storage Technologies (2008)Google Scholar
  13. 13.
    Zhao, H., Jin, P.Q., Yang, P.Y., et al.: BPCLC: An Efficient Write Buffer Management Scheme for Flash-Based Solid State Disks. International Journal of Digital Content Technology and its Applications 4(6), 123–133 (2010)CrossRefGoogle Scholar
  14. 14.
    Ma, D.Z., Feng, J.H., Li, G.L.: LazyFTL: A Page-level Flash Translation Layer Optimized for NAND Flash Memory. In: SIGMOD 2011 (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Junjie Wang
    • 1
  • Lihua Yue
    • 1
  • Peiquan Jin
    • 1
  • Rui Wang
    • 1
  1. 1.School of Computer Science and TechnologyUniversity of Science and Technology of ChinaHefeiChina

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