h-Buffer: An Adaptive Buffer Management Scheme for Flash-Based Storage Devices

  • Rui Wang
  • Lihua Yue
  • Peiquan Jin
  • Junjie Wang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7240)


Due to the limitations of flash memory, such as asymmetric I/O latencies and not-in-place update, there are two kinds of buffer replacement algorithms: page-clustered policy and group-clustered policy. That the former one organizes pages at page-level makes it easy to deal with hot pages, but shows a bad performance when the buffer size is large enough. The latter one organizes pages at group-level, which usually ignores the read request from the host as the RAM size inside SSDs (Solid State Disks) is limited. However, as the read/write latency for flash memory is about 1:10, and most of desk and server application programs are read-intensive, applying a small portion of buffer space for some hot clean pages will benefit most. In this paper, we propose such a buffer management scheme called h-Buffer with three lists. Applying less than 7.125% of the buffer size for clean pages, h-Buffer considers both the write and read requests by the adoption of a replacement policy, a write-back policy and a HL (hot list) compensating policy. Unlike certain existing algorithms, it does not only consider the recency and frequency of page references, but also interacts with the buffer capacities and FTL timely. Experiment results show that the erase count, write count, read count and run time of h-Buffer decrease 50% over traditional algorithms on average.


Buffer Size Read Count Flash Memory Replacement Policy Read Request 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Wu, C.H., Kuo, T.W.: An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems. In: Proc. of IEEE/ACM ICCAD, pp. 601–606 (2006)Google Scholar
  2. 2.
    Xiang, X., Yue, L., et al.: A Reliable B-Tree Implementation over Flash Memory. In: Proc. of ACM SAC, pp. 1487–1491 (2008)Google Scholar
  3. 3.
    Samsung Electronics, K9XXG08UXA.1G X8 Bit/ 2G X8 Bit/ 4G X8 Bit NAND Flash Memory (2006)Google Scholar
  4. 4.
    Intel Corporation, Understanding the Flash Translation Layer (FTL) Specification, Technical Report AP-684 (1998)Google Scholar
  5. 5.
    Kim, J., Kim, J.M., Noh, S.H., et al.: A Space-Efficient Flash Translation Layer for Compact-Flash Systems. IEEE Trans. on Consumer Electronics 48(2), 366–375 (2002)CrossRefGoogle Scholar
  6. 6.
    Park, S.-Y., Jung, D., Kang, J.-U., Kim, J.-S., Lee, J.: CFLRU: A Replacement Algorithm for Flash Memory. In: CASES 2006, pp. 234–241. ACM (2006)Google Scholar
  7. 7.
    Li, Z., Jin, P., et al.: CCF-LRU: A New Buffer Replacement Algorithm for Flash Memory. IEEE Transactions on Consumer Electronics, 1351–1359 (2009)Google Scholar
  8. 8.
    Jin, P., Ou, Y., Harder, T., Li, Z.: AD-LRU: An Efficient Buffer Replacement Algorithm for Flash-Based Databases. Data & Knowledge Engineering (2011)Google Scholar
  9. 9.
    Kim, H., Ahn, S.: BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In: Proc. Sixth USENIX Conf. File and Storage Technologies, pp. 239–252. FAST (2008)Google Scholar
  10. 10.
    Jo, H., Kang, J.-U., Park, S.-Y., et al.: FAB: Flash-Aware Buffer Management Policy for Portable Media Players. IEEE Trans. Consumer Electronics, 485–493 (2006)Google Scholar
  11. 11.
    Kang, S., Park, S., Jung, H., et al.: Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices. IEEE Trans. Computers, 744–758 (2009)Google Scholar
  12. 12.
    Chang, L.-P., Su, Y.-C.: Plugging Versus Logging: A New Approach to Write Buffer Management for Solid-State Disks. In: DAC, pp. 23–28. ACM (2011)Google Scholar
  13. 13.
    Bucy, J.S., Schindler, J., et al.: The DiskSim Simulation Environment Version 4.0 Reference Manual, Carnegie Mellon University Technical Report (2008)Google Scholar
  14. 14.
    Kim, J., Kim, J.M., Noh, S.H., et al.: A Space- Efficient Flash Translation Layer for Compact Flash Systems. IEEE Trans. Consumer Electronics, 366–375 (2002)Google Scholar
  15. 15.
    Lee, S.-W., Park, D.-J., Chung, T.-S., et al.: A Log Buffer Based Flash Translation Layer Using Fully Associative Sector Translation. ACM Trans. Embedded Computing Systems, 436–453 (2007)Google Scholar
  16. 16.
    Park, C., Cheon, W., Kang, J., Roh, K., Cho, W., Kim, J.-S.: A reconfgurable ftl architecture for nand fash-based applications. ACM Trans. Embed. Comput. Syst. 7(4), 1–23 (2008)CrossRefGoogle Scholar
  17. 17.
    Jin, P., Su, X., Li, Z., Yue, L.: A Flexible Simulation Environment for Flash-aware Algorithms. In: Proc. of CIKM 2009, demo. ACM Press (2009)Google Scholar
  18. 18.
    Ou, Y., Harder, T., Jin, P.: CFDC: a flash-aware replacement policy for database buffer management. In: Science And Technology (DaMoN), pp. 15–20. ACM (2009)Google Scholar
  19. 19.
    Lv, Y., Cui, B., He, B., et al.: Operation-Aware Buffer Management in Flash-based Systems. In: SIGMOD, pp. 12–16. ACM (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Rui Wang
    • 1
  • Lihua Yue
    • 1
  • Peiquan Jin
    • 1
  • Junjie Wang
    • 1
  1. 1.School of Computer Science and TechnologyUniversity of Science and Technology of ChinaHefeiChina

Personalised recommendations