Genetic Optimization of Interval Type-2 Fuzzy Systems for Hardware Implementation on FPGAs
This chapter proposes a method for the design of a Type-2 Fuzzy Logic Controller (FLC-T2) and a Type-1 Fuzzy Logic Controller (FLC-T1) using Genetic Algorithms. The two controllers were tested with different levels of uncertainty to Regulate Speed in a Direct Current Motor (ReSDCM). The controllers were synthesized in Very High Description Language (VHDL) code for a Field Programmable Gate Array (FPGA), using the Xilinx System Generator (XSG) of Xilinx ISE and Matlab-Simulink. Comparisons were made between the FLC-T1 versus FLC-T2 in VHDL code and also with a Proportional Integral Differential (PID) Controller, to ReSDCM. To evaluate the difference in performance of the three types of controllers, the t-student statistical test was used.
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