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Design of SENIOR: A Case Study Using \(\mathfrak{NoGap}\)

  • Per Karlström
  • Wenbiao Zhou
  • Dake Liu
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 156)

Abstract

The design and implementation of a new Application Specific Instruction-set Processor(ASIP) processor is usually the result of a substantial design effort, more details about the Application Specific Instruction-set Processor (ASIP) design process can be found in [10]. There are a number of different software tools that relaxes the design effort in one way or another. However all these tools forces the designer into a predefined architecture template. This limitation in design flexibility often makes designers of novel ASIP processors and programmable accelerators revert back to an Hardware Description Language (HDL), e.g. Verilog or VHDL. HDLs offers full design flexibility at the register transfer level, but the flexibility comes at the cost of increased design complexity. All details, e.g. register forwarding and/or pipeline control, has to be handled manually.

Keywords

Data Path Register Transfer Level Pipeline Architecture Hardware Description Language Register Forwarding 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag GmbH Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Department of EELinköping UniversityLinköpingSweden

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