Modern three-dimensional (3D) designs, in which the active devices are placed in multiple layers using 3D integration technologies, are helping to maintain the validity of Moore’s law in today’s nano era. In this chapter, an overview of technologies and physical design in the new 3-dimensional context is presented. A survey of modern 3D integration technologies, such as 3D packages and 3D integrated circuits, is given first. The author then investigates the physical design steps of floorplanning, placement and routing to identify the new design challenges and solutions of 3D nanoscale circuits.


Physical Design Wafer Level Total Wire Length Circuit Layer Routability Prediction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author would like to thank Robert Fischbach and Tilo Meister for their contributions to this work.


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© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.Institute of Electromechanical and Electronic DesignTechnische Universität DresdenDresdenGermany

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