System Integration by Advanced Electronics Packaging

Chapter

Abstract

This chapter presents a review of the status and the trends of system integration by electronics packaging. At first an analysis of the system drivers will be given and the requirements for System in Package (SiP), followed up by More-than-Moore approaches leading to Hetero-System-Integration. One focus of this chapter will lie on the three-dimensional (3D) integration in electronic packages, their assembly and interconnection technologies. This type of system integration has significant advantages for higher density of functions, smaller sizes and higher clock rates. A second focus of this chapter is directed towards challenges for materials of advanced electronics packaging.

Keywords

Solder Bump Wafer Level Thermal Interface Material Through Silicon Vias Isotropic Conductive Adhesive 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Ang, X.F., Lin, A.T., Wei, J., Chen, Z., Wong, C.C.: Low temperature copper–copper thermocompression bonding. In: Proceedings of the 10th Electronics Packaging Technology Conference (EPTC), pp. 399–404. Singapore (2008)Google Scholar
  2. 2.
    Aryasomayajula, L., Rieske, R., Wolter, K.J.: Application of copper-carbon nanotubes composite in packaging interconnects. In: Proceedings of the 34th International Spring Seminar on Electronics Technology (2011)Google Scholar
  3. 3.
    Beelen-Hendrikx, C.: Trends in IC packaging. In: Proceedings of the 17th European Microelectronics and Packaging Conference (EMPC), pp. 1–8. Rimini, Italy (2009)Google Scholar
  4. 4.
    Beica, R.: Advanced metallization for 3D integration. In: Proceedings of the 10th Electronics Packaging Technology Conference, pp. 212–218. Singapore (2008)Google Scholar
  5. 5.
    Beyne, E.: The rise of the 3rd dimension for system integration. In: Proceedings of the 9th International Interconnect Technology Conference, pp. 1–5. Burlingame, USA (2006)Google Scholar
  6. 6.
    Beyne, E.: Solving technical and economical barriers to the adoption of through-Si-via 3D integration. In: Proceedings of the 10th Electronics Packaging Technology Conference (EPTC), pp. 29–34. Singapore (2008)Google Scholar
  7. 7.
    Chen, Q., Zhang, D., Wang, Z., Liu, L., Lu, J.: Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding. In: Proccedings of the 61st Electronic Components and Technology Conference (ECTC), pp. 1–6. Orlando, FL, USA (2011)Google Scholar
  8. 8.
    Cognetti, C.: The impact of semiconductor packaging technologies on system integration—an overview. In: Proceedings of the 35th European Solid-State Circuit Conference, pp. 23–27. Athen, Greece (2009)Google Scholar
  9. 9.
    Combs, J.: Printed Circuit Handbook, 6th edn. McGraw-Hill, New York (2007)Google Scholar
  10. 10.
    DISCO Cooperation: Dicing before grinding process. http://is01.disco.co.jp/psc/aphp.nsf/0/F25F83635A938BAD49256FE3001E5987
  11. 11.
    Gerber, M., Beddingfield, C., O’Connor, S., Yoo, M., Lee, M., Kang, D., Park, S., Zwenger, C., Darveaux, R., Lanzone, R.K.P.: Next generation fine pitch cu pillar technology—enabling next generation silicon nodes. In: Proccedings of the 61st Electronic Components and Technology Conference (ECTC), pp. 612–618. Orlando, FL, USA (2011)Google Scholar
  12. 12.
    Graf, M., Eychmüller, A., Wolter, K.J.: High aspect ratio metallic nanowire arrays by pulsed electrodeposition. In: Proceedings of the 11th International Conference on Nanotechnology. Portland OR, USA (2011)Google Scholar
  13. 13.
    Greig, W.: Integrated Circuit Packaging, Assembly and Interconnects. Springer, New York (2007)Google Scholar
  14. 14.
    Heimann, M., Meißner, F., Schönecker, A., Endler, I., Wolter, K.J.: Nano-scaled functional layers for current and heat transport in electronics packaging. In: Proccedings of the 2nd Electronics System-Integration Technology Conference (ESTC), pp. 333–338. Greenwich, London (2008)Google Scholar
  15. 15.
    International Technology Roadmap for Semiconductors (ITRS): Assembly and packaging, edition 2007. Technical report, Semiconductor Industry Association. http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_Assembly.pdf (2007)
  16. 16.
    International Technology Roadmap for Semiconductors (ITRS): The next steps in assembly and packaging. Technical Report, Semiconductor Industry Association. http://www.itrs.net/links/2007ITRS/LinkedFiles/AP/AP_Paper.pdf (2007)
  17. 17.
    International Technology Roadmap for Semiconductors (ITRS): System driver, edition 2009. Technical Report, Semiconductor Industry Association (2009)Google Scholar
  18. 18.
    Jiang, T.S.L.: 3D integration-present and future. In: Proceedings of the 10th Electronics Packaging Technology Conference (EPTC), pp. 373–378. Singapore (2008)Google Scholar
  19. 19.
    Kettner, P., Burggraf, J., Kim, B.: Thin wafer handling and processing—results achieved and upcoming tasks in the field of 3D and TSV. In: Proceedings of the 11th Electronic Packaging and Technology Conference (EPTC), pp. 787–789. Singapore (2009)Google Scholar
  20. 20.
    Knickebocker, J.U., Andry, P.S., Dang, B., Horton, R.R., Patel, C.S., Polastre, R.J., Sakuma, K., Sprogis, E.S., Trang, C.K., Webb, B.C., Wright, S.L.: 3D silicon integration. In: Proceedings of the 58th Electronic Components and Technology Conference (ECTC), pp. 538–543. Orlando FL, USA (2008)Google Scholar
  21. 21.
    Li, Z.X., Gupta, M.: High strength lead-free composite solder materials using nano-\({\rm {Al}}_{2}{\rm {O}}_{3}\) as reinforcement. Adv. Eng. Mater. 7(11), 1049–1053 (2005)Google Scholar
  22. 22.
    Lin, W., Wong, C.P.: Applications of carbon nanomaterials as electrical interconnects and thermal interface material. In: Wond, C.P., Moon, K.-S., Li, Y. (eds.) Nano-Bio-Electronic, Photonic and MEMS Packaging. Springer, Heidelberg (2010)Google Scholar
  23. 23.
    Morris, J.E. (ed.): Nanopackaging. Springer, New York (2008)Google Scholar
  24. 24.
    Panchenko, I., Wolter, K.J.: Interconnect technology for 3D chip integration. In: Proccedings of the Electronics and Nanotechnology Conference. Kyiv, Ukraine (2011)Google Scholar
  25. 25.
    Röllig, M.: Beiträge zur Bestimmung von Mechanischen Kennwerten an Produktkonformen Lotkontakten Der Elektronik. Verlag Dr. Markus A. Detert, New Yok (2009)Google Scholar
  26. 26.
    Roozeboom, F., Blauw, M., Lamy, Y., Grunsven, E., Dekkers, W., Verhoeven, J., Heuvel, E., Drift, E., Kessels, E., Sanden, R.: Deep reactive ion etching of through silicon vias. In: Garrou, Ph., Bower, Ch., Ramm, P. (eds.) Handbook of 3D Integration, vol. 1. Wiley-VCH Verlag, Weinheim (2008)Google Scholar
  27. 27.
    Sapatnekar, S.: Handbook of 3D Integration, Chap. Computer-Aided Design for 3D Circuits at the University of Minnesota. Wiley-VCH Verlag, Weinheim (2008)Google Scholar
  28. 28.
    Shi, Y.W., Liu, J., Xia, Z.D., Lei, Y.P., Guo, F., Li, X.: Creep property of composite solders reinforced by nano-sized particles. J. Mater. Sci. Mater. Electron. 19(4), 349–356 (2008)CrossRefGoogle Scholar
  29. 29.
    Sukumaran, V., Bandyopadhyay, B., Chen, Q., Kumbhat, N., Liu, F., Pucha, R., Sato, Y., Watanabe, M., Kitaoka, K., Ono, M., Suzuki, Y., Karoui, C., Nopper, C., Swaminathan, M., Sundaram, V., Tummala, R.: Design, fabrication and characterization of low-cost glass interposers. In: Proccedings of the 61st Electronic Components and Technology Conference (ECTC), pp. 583–588. Orlando FL, USA (2011)Google Scholar
  30. 30.
    Tan, C.S., Gutmann, R.J., Reif, L. (eds.): Wafer Level 3-D ICs Process Technolgy. Springer, London (2008)Google Scholar
  31. 31.
    Vempati, S.R., Ho, S.W., Lee, W.S.V., Li, H.Y., Liao, E., Ranganathan, N., Chai, T.C., Xiaowu, Z., Pinjala, D.: TSV interposer fabrication for 3D IC packaging. In: Proccedings of the 11th Electronics Packaging Technology Conference (EPTC), pp. 431–437. Singapore (2009)Google Scholar
  32. 32.
    Wakuda, D., K., K., Suganuma, K.: Properties of Ag nanoparticle paste for room temperature bonding. In: Proccedings of the 59th Electronic Components and Technology Conference (ECTC), pp. 1557–1562. San Diego CA, USA (2009)Google Scholar
  33. 33.
    Wong, C.P., Moon, K.-S.: Nanomaterials for microelectronic and bio-packaging. In: Wong, C.P., Moon, K.-S., Li Y. (eds.) Nano-Bio-Electronic, Photonic and MEMS Packaging. Springer, Berlin (2010)Google Scholar
  34. 34.
    Xie, Y., Cong, J., Sapatnekar, S.: Three-Dimensional Integrated Circuit Design. Springer, New York (2010)Google Scholar
  35. 35.
    Yannou, J.M.: SiP and WLP-CSP trends: State-of-the-art and future trends. In: Proceedings of the 2nd Electronics Systemintegration Technology Conference (ESTC), pp. 3–6. London (2008)Google Scholar
  36. 36.
    Yoon, S., Yang, D., Koo, J., Padmanathan, M., Carson, F.: 3D TSV processes and its assembly/packaging technology. In: Proceedings of the International Conference on 3D System Integration of the Institute of Electrical and Electronics Engineering, pp. 1–5. San Francisco, USA (2009)Google Scholar
  37. 37.
    Zentralverband Elektrotechnik- und Elektronikindustrie: Mikroelektronik—Trendanalyse bis 2013. Technical Report, ZVEI (2010)Google Scholar
  38. 38.
    Zerna, T.: Aufbau- und Verbindungstechnik für Elektronik-Baugruppen der Höchstintegration. Verlag Dr. Markus A. Detert, New York (2008)Google Scholar
  39. 39.
    Zoschke, K., Wolf, J., Lopper, C., Kuna, I., Jürgensen, N., Glaw, V., Samulewicz, K., Röder, J., Wilke, M., Wünsch, O., Klein, M., Suchodoletz, M., Oppermann, H., Braun, T., Wieland, R., Ehrmann, O.: TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules. In: Proccedings of the 61st Electronic Components and Technology Conference (ECTC), pp. 838–843. Orlando FL, USA (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.Electronic Packaging LaboratoryTechnische Universität DresdenDresdenGermany

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