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Very Compact Hardware Implementations of the Blockcipher CLEFIA

  • Toru Akishita
  • Harunaga Hiwatari
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7118)

Abstract

The 128-bit blockcipher CLEFIA is known to be highly efficient in hardware implementations. This paper proposes very compact hardware implementations of CLEFIA-128. Our implementations are based on novel serialized architectures in the data processing block. Three types of hardware architectures are implemented and synthesized using a 0.13 μm standard cell library. In the smallest implementation, the area requirements are only 2,488 GE, which are about half of the previous smallest implementation as far as we know. Furthermore, only additional 116 GE enable to support decryption.

Keywords

blockcipher CLEFIA compact hardware implementation ASIC 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Toru Akishita
    • 1
  • Harunaga Hiwatari
    • 1
  1. 1.Sony CorporationShinagawa-kuJapan

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