The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
Heterogeneous multicore architectures pose specific challenges regarding their programmability and they require smart mapping schemes to make efficient use of different processing elements. Various criteria can drive this mapping, such as computational intensity, memory requirements, and area consumption. In order to facilitate this complex mapping task, there is a clear need for tools that investigate the use of such critical resources, like memory and hardware area. For this purpose, we developed the Q 2 profiling framework. It consists of two main parts: an advanced memory access profiling toolset, which provides detailed information on the runtime memory access patterns of an application and a statistical modeling component, which makes hardware area predictions early in the design phase based on software metrics. These tools are integrated using a partitioning methodology. We demonstrate the effectiveness of our framework using three applications in our experiments. One application is further detailed in a case study to illustrate the use of our methodology. Experimental results show application speedup of up to 2.92×.
KeywordsMemory Access Memory Block Call Graph Code Segment General Purpose Processor
Unable to display preview. Download preview PDF.
- 1.Canny Edge Detector, Image Analysis Research Lab., USF, http://marathon.csee.usf.edu/edge/edge_detection.html
- 2.Baleani, M., et al.: HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. In: CODES 2002, pp. 151–156 (2002)Google Scholar
- 3.Luk, C., et al.: Pin: building customized program analysis tools with dynamic instrumentation. In: PLDI 2005, pp. 190–200 (2005)Google Scholar
- 4.Supplee, L.M., et al.: MELP: the new federal standard at 2400 bps. In: IEEE International Conference on Acoustics Speech and Signal Processing, pp. 1591–1594 (1997)Google Scholar
- 7.Experts, A.A.C.: Cosy: Compiler system, http://www.ace.nl/
- 8.Gohringer, D., et al.: A design methodology for application partitioning and architecture development of reconfigurable multiprocessor systems-on-chip. In: FCCM 2010, pp. 259–262 (2010)Google Scholar
- 11.Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., Stockwood, J.: Hardware-software co-design of embedded reconfigurable architectures. In: DAC 2000, pp. 507–512 (2000)Google Scholar
- 12.Meeuws, R.J.: A Quantitative Model for Hardware/Software Partitioning. Master’s thesis, Delft University of Technology, Delft, Netherlands (2007)Google Scholar
- 13.Meeuws, R.J., Galuzzi, C., Bertels, K.: High level quantitative hardware prediction modeling using statistical methods. In: SAMOS 2011, pp. 140–149 (2011)Google Scholar
- 15.Santambrogio, M., et al.: A novel SoC design methodology combining adaptive software and reconfigurable hardware. In: ICCAD 2007, pp. 303–308 (2007)Google Scholar
- 16.Wang, G., Gong, W., Kastner, R.: Application partitioning on programmable platforms using the ant colony optimization. Journal of Embedded Computing 2(1), 119–136 (2006)Google Scholar