Efficient Communication for FPGA Clusters
Efficient communication between nodes is critical for achieving high performance in a computer cluster. Based on a dedicated inter-accelerator network, we enhance this communication with advanced networking functions, such as broadcasting and priority routing. This work enables decoupling user applications from physical network implementations, improving overall communication efficiency and modularity. A performance model is introduced taking into account application and platform specific parameters. Experiments are performed for various network configurations and application patterns. The results show up to a 55% reduction of communication time when employing our approach.
KeywordsTransmission Time Heterogeneous Cluster Hardware Accelerator Large Data Volume Packet Buffer
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- 1.InfiniBand architecture specification release 1.2.1. White Paper (2010)Google Scholar
- 2.TOP 500 supercomputer sites (2010), http://www.top500.org/lists/2011/06
- 3.Baxter, R., et al.: Maxwell - a 64 FPGA supercomputer. In: Proc. Conference on Adaptive Hardware and Systems (AHS), pp. 287–294 (2007)Google Scholar
- 4.Denholm, S., Tsoi, K.H., Pietzuch, P., Luk, W.: CusComNet: A customisable network for reconfigurable heterogeneous clusters. In: Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, ASAP (2011)Google Scholar
- 5.Lindtjrn, O., Clapp, R.G., Pell, O., Mencer, O., Flynn, M.J.: Surviving the end of scaling of traditional micro processors in HPC. IEEE HOT CHIPS 22 (2010)Google Scholar
- 6.Sass, R., et al.: Reconfigurable computing cluster (RCC) project: Investigating the feasibility of FPGA-based petascale computing. In: Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 127–140 (2007)Google Scholar