Reconfigurable Multicore Architecture for Dynamic Processor Reallocation

  • Annie Avakian
  • Natwar Agrawal
  • Ranga Vemuri
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7199)

Abstract

One of the challenges of multicore design is providing data quickly to all the processor cores running on a system. Recent proposals of hybrid and reconfigurable interconnect architectures try to take advantage of data locality to a certain extent by grouping processors that work on the same data. In this paper, we propose migrating processors instead of data to take advantage of data locality. This is realized by implementing a reconfigurable interconnect that allows reassignment of processor cores to different routers at runtime. We present the proposed architecture in detail, show a segmented hardware implementation of the proposed architecture, and discuss experimental results using PARSEC benchmark showing the performance gains of the proposed architecture. Our results show a gain in average L2 access time of up to 24% when implementing the proposed architecture compared to a hybrid architecture without reconfiguration. Finally we present area and performance data based on a detailed Verilog model and synthesis of the proposed architecture.

Keywords

Clock Cycle Processor Core Hybrid Architecture Gate Count Multicore Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Duato, J., Yalamanchili, S., Lionel, N.: Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc., San Francisco (2002)Google Scholar
  2. 2.
    Foglia, P., Panicucci, F., Prete, C.A., Solinas, M.: Analysis of performance dependencies in nuca-based cmp systems. In: Symposium on Computer Architecture and High Performance Computing, pp. 49–56 (2009)Google Scholar
  3. 3.
    Dybdahl, H., Stenstrom, P.: An adaptive shared/private nuca cache partitioning scheme for chip multiprocessors. In: HPCA 2007: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp. 2–12. IEEE Computer Society, Washington, DC, USA (2007)CrossRefGoogle Scholar
  4. 4.
    Das, R., Eachempati, S., Mishra, A.K., Narayanan, V., Das, C.R.: Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps, pp. 175–186 (February 2009)Google Scholar
  5. 5.
    Avakian, A., Nafziger, J., Panda, A., Vemuri, R.: A reconfigurable architecture for multicore systems. In: 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1–8. IEEE (2010)Google Scholar
  6. 6.
  7. 7.
  8. 8.
  9. 9.
    Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: PACT 2008: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72–81. ACM, New York (2008)Google Scholar
  10. 10.
    Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and management of 3d chip multiprocessors using network-in-memory. SIGARCH Comput. Archit. News 34(2), 130–141 (2006)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Annie Avakian
    • 1
  • Natwar Agrawal
    • 1
  • Ranga Vemuri
    • 1
  1. 1.School of Electronics and Computing SystemsUniversity of CincinnatiUSA

Personalised recommendations