Abstract
We propose and analyze novel Ternary logic circuits targeting an asynchronous Null Convention Logic (NCL) pipeline where the Null value (i.e. Data not valid) is used to make the pipeline self-synchronizing and delay insensitive. A balanced Ternary logic system is used, in which the logic set {High Data, Null, Low Data} maps to voltage levels {+VDD, 0V, -VDD}. Low power circuits such as Ternary to Binary converter, DATA/NULL Detector and Ternary Register are described based a 45nm SOI process technology that offers multiple simultaneous transistor thresholds.
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Andrawes, S., Beckett, P. (2012). Null Convention Logic Circuits Using Balanced Ternary on SOI. In: Gaol, F., Nguyen, Q. (eds) Proceedings of the 2011 2nd International Congress on Computer Applications and Computational Science. Advances in Intelligent and Soft Computing, vol 145. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28308-6_12
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DOI: https://doi.org/10.1007/978-3-642-28308-6_12
Publisher Name: Springer, Berlin, Heidelberg
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