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Multithreaded Peripheral Processor for a Multicore Embedded System

  • Horia V. Caprita
  • Mircea Popa
Part of the Topics in Intelligent Engineering and Informatics book series (TIEI, volume 1)

Abstract

Multithreaded and multicore architectures represent a good solution used for increasing of parallelism degree exploited in modern computing systems and they can reduce the power dissipated in the chip by using low-frequency clock signals. These advantages recommend these parallel architectures for integration in the embedded systems, with restrictions imposed by the relatively small integration area. Particularities of embedded applications require hardware support able to handling in real time the peripheral interrupt requests. The performance of this hardware influences the performance of the entire parallel system. The current trend is to integrate in one microcontroller more processors used for general purpose application and a processor used for peripherals related applications (like interrupt services). In this chapter we present a peripheral processor architecture implemented in multithreaded technology, processor able to handle more tasks concurrently. Parallel execution of these peripheral tasks, in conjunction with a multicore processor used in processing of the general application (e.g. operating system), will lead to an increase in overall performance of the embedded system.

Keywords

Register File Multicore Processor Main Thread Multicore Architecture Interrupt Handler 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Burger, D., Austin, T.M.: The SimpleScalar Tool set version 2.0. ACM SIGARCH Comput. Archit. News 25, 13–25 (1997); doi:10.1145/268806.268810CrossRefGoogle Scholar
  2. 2.
    Caprita, H.V., Popa, M.: Design methods of multithreaded architectures for multicore microcontrollers. In: Proc. 6th IEEE Int. Symp. Appl. Comput. Intell. Inform., Timisoara, Romania, pp. 427–432 (2011); doi: 10.1109/SACI.2011.5873041Google Scholar
  3. 3.
    Chappell, R.S., Stark, J., Kim, S.P., Reinhardt, S.K., Patt, Y.N.: Simultaneous Subordinate Microthreading (SSMT). In: Proc. 26th Annu. Int. Symp. Comput. Archit., Atlanta, GA, USA, pp. 186–195 (1999); doi: 10.1145/300979.300995Google Scholar
  4. 4.
    Giorgi, R., Popovic, Z., Puzovic, N.: Implementing fine/Medium grained TLP support in a many-core architecture. In: Proc. 9th Int. Workshop Embed Comput. Syst., Heidelberg, Germany, pp. 78–87 (2009); doi: 10.1007/978-3-642-03138-0_9Google Scholar
  5. 5.
    Ravotto, D., Sanchez, E., Sonza Reorda, M., Squillero, G.: Design validation of multithreaded architectures using concurrent threads evolution. In: Proc. 22nd Annu. Symp. Integr. Circuits Syst. Des., Natal, Brazil (2009); doi: 10.1145/1601896.1601964Google Scholar
  6. 6.
    Redstone, J., Eggers, S., Levy, H.: Mini-threads: Increasing TLP on small-scale SMT processors. In: Proc 9th Int. Symp. High Perform. Comput. Archit., Anaheim, CA, USA, pp. 19–30 (2003)Google Scholar
  7. 7.
    Sibai, F.N.: Evaluating the performance of single and multiple core processors with PCMARK®05 and benchmark analysis. ACM SIGMETRICS Perform. Eval. Rev. 35, 62–71 (2008)CrossRefGoogle Scholar
  8. 8.
    Spracklen, L., Abraham, S.G.: Chip multithreading: Opportunities and challenges. In: Proc. 11th Int. Symp. High Perform. Comput. Archit., San Francisco, CA, USA, pp. 248–252 (2005); doi: 10.1145/1364644.1364647Google Scholar
  9. 9.
    Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. In: Proc. 23rd Annu. Int. Symp. Comput. Archit., Philadelphia, PA, USA, pp. 191–202 (1996); doi: 10.1145/232973.232993Google Scholar
  10. 10.
    Tullsen, D.M., Brown, J.A.: Handling long-latency loads in a simultaneous multithreading processor. In: Proc. 34th Annu. ACM/IEEE Int. Symp. Micro., Austin, TX, USA, pp. 318–327 (2001)Google Scholar
  11. 11.
    Uhrig, S.: Evaluation of different multithreaded and multicore processor configurations for SoPC. In: Proc. 9th Int. Workshop Embed Comput. Syst., Heidelberg, Germany, pp. 68–77 (2009); doi: 10.1007/978-3-642-03138-0_8Google Scholar
  12. 12.
    Ungerer, T., Robic, B., Silc, J.: A survey of processors with explicit multithreading. ACM Comput. Surv. 35, 29–63 (2003); doi:10.1145/641865.641867CrossRefGoogle Scholar
  13. 13.
    Wei, H., Stan, M.R., Gurumurthi, S., Ribando, R.J., Skadron, K.: Interaction of scaling trends in processor architecture and cooling. In: Semicond. Therm. Meas. Manag. Symp., Santa Clara, CA, USA, pp. 198–204 (2010); doi:10.1109/STHERM.2010.5444290Google Scholar

Copyright information

© Springer-Verlag GmbH Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.Faculty of Engineering“Lucian Blaga” University of SibiuSibiuRomania
  2. 2.Faculty of Automation and Computers“Politehnica” University of TimisoaraTimisoaraRomania

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