Verifying a Logic Design

  • Shimon P. Vingron


The problem considered in this chapter is this: Having designed an asynchronous circuit according to a given word-recognition tree, or flow table, we next want to verify our logic design by developing a minimal length events graph with which to completely test the circuit’s input–output behaviour. In the literature, this is usually referred to as functional testing. In general, the problem is seen as unsolvable. Mead and Conway (1980) put it this way: ‘Complete functional testing of complex systems with internal sequencing is not possible in general, and most integrated system chips manufactured, even at 1978 levels of complexity, are not economically testable for even a small fraction of their possible internal states.’


  1. Brzozowski, J.A., Yoeli, M.: Digital Networks. Prentice Hall, Englewood Cliffs (1976)Google Scholar
  2. Brzozowski, J.A., Seger, C.-J.H.: Asynchronous Circuits. Springer, New York (1995)CrossRefGoogle Scholar
  3. Caldwell, S.H.: Switching Circuits and Logic Design. Wiley, New York (1958)Google Scholar
  4. Clare, C.R.: Designing Logic Systems using State Machines. McGrew-Hill Book Company, New York (1973)Google Scholar
  5. Dietmeyer, D.L.: Logic Design of Digital Systems. Allyn and Bacon, Boston (1971)MATHGoogle Scholar
  6. Eilenberg, S., Elgot, C.C.: Recursiveness. Academic Press, New York (1970)MATHGoogle Scholar
  7. Fasol, K.H., Vingron, P.: Synthese Industrieller Steuerungen. R. Oldenbourg Verlag, München (1975)MATHGoogle Scholar
  8. Harrison, M.A.: Introduction to Switching and Automata Theory. McGraw-Hill Book Company, New York (1965)MATHGoogle Scholar
  9. Kohavi, Z.: Switching and Finite Automata Theory. McGraw-Hill Book Company, New York (1970)MATHGoogle Scholar
  10. Krieger, M.: Basic Switching Circuit Theory. McGraw-Hill Book Company, New York (1969)Google Scholar
  11. McCluskey, E.J.: Logic Design Principles. Prentice Hall, London (1986)Google Scholar
  12. Mead, C., Conway, L.: Introduction to VLSI Systems. Addison-Wesley, Reading Massachusetts (1980)Google Scholar
  13. Muroga, S.: Logic Design and Switching Theory. Wiley, New York (1979)MATHGoogle Scholar
  14. Pessen, D.W.: Ìndustrial Automation. Wiley, New York (1989)Google Scholar
  15. Unger, S.H.: Asynchronous Sequential Switching Circuits. Wiley, New York (1969)Google Scholar
  16. Vingron, S.P.: Switching Theory. Springer, Berlin (2004)Google Scholar
  17. Zander, H.-J.: Entwurf von Folgeschaltungen. VEB Verlag Technik, Berlin (1974) Selected Papers Google Scholar
  18. Ashenhurst, R.A.: The decomposition of switching functions. In: Proceedings of an International Symposium on the Theory of Switching, April 2–5, 1957. Annals of the Compotation Laboratory of Harvard University, vol. 29, pp. 74–116. Harvard University Press (1959)Google Scholar
  19. Huffman, D.A.: The synthesis of sequential switching circuits. J. Frankl. Inst. 257:161–190 (1954) and 275–303 (1954)Google Scholar
  20. Huffman, D.A.: A study of memory requirements of sequential switching circuits. Massachusetts Institute of Technology, Research Laboratory of Electronics, Technical Report No. 293, April 1955Google Scholar
  21. Huffman, D.A.: The design and use of Hazard-Free switching networks. J. Assoc. Comput. Mach. 4:47–62 (1957)MathSciNetCrossRefGoogle Scholar
  22. Karnaugh, M.: The map method for synthesis of combinational logic circuits. Trans. AIEE, Part I, 72(9):593–599 (1953)Google Scholar
  23. McCluskey, E.J.: Minimisation of boolean functions. Bell Syst. Tech. J. 35(6):1417–1445 (1956)MathSciNetGoogle Scholar
  24. Mealy, G.H.: A method for synthesizing sequential circuits. Bell Syst. Tech. J. 34(5):1045–1079 (1955)MathSciNetGoogle Scholar
  25. Medvedev, I.T.: On a class of events representable in a finite automaton, pp. 385–401. Avtomaty, Moscow (1956). English translation in MIT Lincoln Laboratory Group Report, pp. 34–73, June 1958Google Scholar
  26. Moore, E.F.: Gedankenexperiments on sequential machines. In: Shannon, C.E., McCarthy, J., Ashby, W.R. (eds.) Automata Studies. Princeton University Press, Princeton (1956)Google Scholar
  27. Quine, W.V.: The problem of simplifying truth functions. Am. Math. Mon. 59:521–531 (1952)MathSciNetMATHCrossRefGoogle Scholar
  28. Quine, W.V.: A way to simplify truth functions. Am. Math. Mon. 63:627–631 (1955)MathSciNetCrossRefGoogle Scholar
  29. Shannon, C.E.: A symbolic analysis of relays and switching circuits. Trans. AIEE 57:713–723 (1938)Google Scholar
  30. Tracey, J.H.: Internal state assignment for asynchronous sequential circuits. IEEE Trans. Electron. Comput. EC-15:551–560 (1966)Google Scholar
  31. Unger, S.H.: Hazards and delays in asynchronous sequential circuits. IRE Trans. Circuit Theory CT-6:12–25 (1959)Google Scholar
  32. Veitch, E.W.: A chart method for simplifying truth functions. Proceedings of Pittsburgh Association for Computing Machinery, University of Pittsburgh, May 1952Google Scholar
  33. Vingron, P.: Coherent design of sequential circuits. IEE Proc. 130E:190–201 (1983)Google Scholar
  34. Zhegalkin, I.I.: The French title of the Russian original is Gégalkin I. I.: ‘Sur le calcul des propositions dans la logique symbolique’. Mat. Sbornik 34:9–28 (1927)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Shimon P. Vingron
    • 1
  1. 1.HinterbrühlAustria

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