Systolic Optimization on GPU Platforms

  • Enrique Alba
  • Pablo Vidal
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6927)


The article presents a systolic algorithm implemented using NVIDIA’s Compute Unified Device Architecture (CUDA). The algorithm works as a general disposition of the elements in a mesh by sinchronously computing basic solutions among processing elements. We have used instances of the Subset Sum Problem for evaluating to study the behavior of the proposed model. The experimental results show that the approach is very efficient, especially for large problem instances and consumes shorter times compared to other algorithms like parallel Genetic Algorithms and Random Search.


Genetic Algorithm Graphic Processing Unit Systolic Array Error Ratio Large Problem Instance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Grama, A., Karypis, G., Kumar, V., Gupta, A.: Introduction to Parallel Computing, 2nd edn. Addison-Wesley, Boston (2003)zbMATHGoogle Scholar
  2. 2.
    Kung, H.T., Leiserson, C.E.: Systolic Arrays (for VLSI). In: Sparse Matrix Proc., pp. 256–282. Academic Press, Orland (1979)Google Scholar
  3. 3.
    Kung, H.T.: Why Systolic Architectures? In: Advanced Computer Architecture, USA, pp. 300–309 (1982/1986)Google Scholar
  4. 4.
    Holland, J.H.: Adaptation in Natural and Artificial Systems. MA, USA (1992)Google Scholar
  5. 5.
    Kung, H.T., Lehman, L.: Systolic (VLSI) arrays for relational database operations. In: Conference on Management of Data, New York, USA, pp. 105–116 (1980)Google Scholar
  6. 6.
    Alba, E.: Parallel Metaheuristics: a New Class of Algorithms. Interscience (2005)Google Scholar
  7. 7.
    Corporation, N.: NVIDIA CUDA Programming Guide, version 1.1. Technical report (November 2007)Google Scholar
  8. 8.
    Chan, H., Mazumder, P.: A systolic architecture for high speed hypergraph partitioning using a genetic algorithm. In: Yao, X. (ed.) AI-WS 1993 and 1994. LNCS, vol. 956, pp. 109–126. Springer, Heidelberg (1995)CrossRefGoogle Scholar
  9. 9.
    Megson, G.M., Bland, I.M.: Synthesis of a systolic array genetic algorithm. In: Proc. 12th Int. Parallel Processing Symp., pp. 316-320 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Enrique Alba
    • 1
  • Pablo Vidal
    • 1
  1. 1.E.T.S.I. InformáticaUniversidad de MálagaMálagaEspaña

Personalised recommendations