SPAD-Based Sensors

  • Edoardo Charbon
  • Matt Fishburn
  • Richard Walker
  • Robert K. Henderson
  • Cristiano Niclass


3D imaging and multi-pixel rangefinding constitute one of the most important and innovative fields of research in image sensor science and engineering in the past years. In rangefinding, one computes the Time-Of-Flight of a ray of light, generated by a mono-chromatic or wide-spectral source, from the source through the reflection of a target object and to a detector. There exist at least two techniques to measure the Time-Of-Flight (TOF): a direct and an indirect technique. In direct techniques (D-TOF), the time difference between a START pulse, synchronized with the light source, and a STOP signal generated by the detector is evaluated. In indirect techniques (I-TOF), a continuous sinusoidal light wave is emitted and the phase difference between outgoing and incoming signals is measured. From the phase difference, the time difference is derived using well-known formulae.


Image Sensor Stop Signal CMOS Technology Depletion Region Ring Oscillator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

1 Introduction

3D imaging and multi-pixel rangefinding constitute one of the most important and innovative fields of research in image sensor science and engineering in the past years. In rangefinding, one computes the Time-Of-Flight of a ray of light, generated by a mono-chromatic or wide-spectral source, from the source through the reflection of a target object and to a detector. There exist at least two techniques to measure the Time-Of-Flight (TOF): a direct and an indirect technique. In direct techniques (D-TOF), the time difference between a START pulse, synchronized with the light source, and a STOP signal generated by the detector is evaluated. In indirect techniques (I-TOF), a continuous sinusoidal light wave is emitted and the phase difference between outgoing and incoming signals is measured. From the phase difference, the time difference is derived using well-known formulae.

Single-photon avalanche diodes (SPADs) or Geiger-mode avalanche photodiodes (GAPDs) are detectors capable of capturing individual photons with very high time-of-arrival resolution, of the order of a few tens of picoseconds. They may be fabricated in dedicated silicon processes or in standard CMOS technologies. Most SPADs generally operate at room temperature, but they may also be cooled for better noise performance. Even though solid-state SPADs implemented in III–V materials exist, and the literature on the subject is extensive, in this chapter, we limit our attention to silicon devices.

Cova and McIntyre started advocating the use of SPADs for fast timing applications in the 1980s [1, 2]. Thanks to their picosecond timing resolution, SPADs are a natural candidate for D-TOF techniques. If one wants a distance resolution of, say, 1 mm, one needs to discriminate light pulses with a resolution of 6.6 ps (a round-trip Time-Of-Flight is assumed). However, such a time uncertainty is not achievable with a room temperature SPAD implemented in any silicon technology. Thus, averaging and multi-measurement techniques must be employed. A common choice is the use of time-correlated single-photon counting (TCSPC). The technique assumes that a START or synchronization signal is always present at the beginning of each measurement cycle, while the STOP signal is provided by the detector, in our case a SPAD, at a much smaller frequency, typically 104–106 smaller than that of the synchronization. If this condition is satisfied—and it is often required to minimize pile-up effects—several thousands of time-of-arrival evaluations are needed for each frame to achieve an accurate Time-Of-Flight measurement. A reverse START-STOP arrangement is also possible, depending upon the architecture of the imager, whereas a higher jitter of the measurement system might incur if high intra-optical-pulses jitter is present in the light source.

SPADs may also be used in I-TOF mode of operation. In this chapter two complementary techniques are presented. The common principle is that of quickly switching the SPAD to divert its output signal appropriately, depending on the time-of-arrival. Indirect detection techniques may also be handled in a completely digital environment, thus simplifying the electronics and control signals and enabling large arrays of pixels to be implemented in standard CMOS technologies.

The chapter is organized as follows. After an introduction to the physical mechanisms underlying SPADs, an overview of SPAD fabrication techniques is given, followed by a detailed description of direct and indirect techniques for Time-Of-Flight measurement; the description is complemented by examples of SPAD array implementations in CMOS and relative characterization. An outlook concludes the chapter.

2 The Physics of SPADs

An avalanche photodiode (APD) is a p-n junction that relies on impact ionization effects to multiply photon-generated electrons and holes. APDs output a pulse of electric current synchronous, with some time uncertainty, to the arrival of a single photon. In APD-based, Time-Of-Flight detectors and image sensors, external circuitry senses and analyzes this current pulse to find the photon’s time-of-arrival, thus inferring the range; this process, known as rangefinding, enables the reconstruction of 3D scenes non-destructively. This section gives an overview of the fundamental mechanisms governing the avalanche pulse, focusing on the factors that contribute to the time uncertainty and ultimately the distance estimation accuracy.

Generally, when electrical engineers think of the I–V characteristics of a p-n junction, they think of the steady state curve, shown in Fig. 1. However, there is a pseudo-steady-state in the breakdown operating condition—a voltage above1 the breakdown voltage can be applied so long as no carriers exist in the diode’s depletion region. As soon as a carrier is injected into the depletion region, impact ionization may cause an avalanche to occur, and the diode will shift operating points to the steady-state curve. Impact ionization’s underlying statistical process, which is dependent on the electric field, material, and ambient conditions, governs the probability that an avalanche will occur. If the electric field magnitude is high enough, then both electrons and holes are expected to cause significant ionization, the avalanche will become self-sustaining, and the avalanche photodiode is operating in Geiger mode.2
Fig. 1

Steady-state I–V characteristics for a p-n junction with Geiger and avalanche mode of operation (left). Passively quenched SPAD (right). VE is known as the excess bias voltage at which a diode must be biased in Geiger mode; it represents the voltage in excess of or above the breakdown voltage VBD. A comparator or inverter is used to shape the output pulse of the detector

If the field magnitude is only sufficient for electrons to cause significant ionization but not holes, the APD is in linear mode. Quantitatively a diode is in Geiger mode when it meets the condition
$$ 1 \le \int_{0}^{W} {\alpha \cdot \exp \left( {\int_{x}^{W} {(\beta - \alpha ){\text{d}}x^{\prime}} } \right)} {\text{ d}}x, $$
with α and β representing the impact ionization rates (per m) of electrons and holes, respectively, and W is the depletion width. The bias at which Eq. (1) is an equality is called the breakdown voltage, V BD. The bias applied to the diode, V OP, exceeds breakdown by a voltage known as excess bias voltage, V E. Henceforth the discussion will be restricted to SPAD technologies [3].

A SPAD is able to detect more than a single carrier by the inclusion of external circuitry, which quenches an avalanche by: sensing an avalanche; lowering the voltage applied to the SPAD; and after some time, raising the applied voltage above the breakdown voltage. The simplest such circuit is a resistor placed in series with the diode, also known as ballast resistor. The circuit works as follows. First, when there are no free carriers in the junction, the applied voltage on the diode is V OP. When light injects a carrier into the junction, impact ionization may or may not cause the rapid build-up of free carriers in a small part of the diode. If significant ionization does not occur and all free carriers are swept out of the depletion region, the incident photon is not detected. If ionization does occur, it will continue until the space-charge phenomena limits the local carrier concentration. The avalanche will spread to other regions of the diode via a multiplication-assisted diffusion process. The decrease in voltage across the diode, dependent on both any parasitic capacitances and the quenching resistor, will eventually reach the excess bias. At this point the diode is quenched—no further current should flow from impact ionization and there are no free carriers in the diode itself. The voltage will then be recharged by the flow of electric current through the quenching resistor into the parasitic capacitances, with the diode being ready to detect another carrier after this dead time [4].

The probability that a single photon’s generated carriers are detected is called the photon detection probability (PDP). A number of factors influence the PDP, including electric field conditions, doping levels, whether electrons or holes primarily initiate avalanches, and the applied voltage. Photons are not the only source of initial carriers; uncorrelated or correlated noise can also cause free carrier injection and undesirable avalanches. Uncorrelated noise sources include: ambient light; tunneling from an electric field that is too high; and fabrication defects which ease valence-to-conduction band transitions, such as thermally generated or tunneling carriers. The last factor, fabrication defects, can also cause afterpulsing, a type of time-correlated noise. Traps in the forbidden energy band can fill, only to release free carriers on the time scale of tens of nanoseconds following an avalanche. Afterpulsing prevents an instant recharge phase in SPADs, and places constraints on the minimum dead time.

There are other sources of correlated noise besides afterpulsing—optical and electrical crosstalk are the most common, but in practice afterpulsing is the dominant type of correlated noise. Whether the initial carrier is photon-generated or not, several factors cause time uncertainty between the injection time and the sense time. The most important timing factor is whether the carrier is generated in the depletion region itself, or if it must diffuse into the depletion region. Carriers that successfully diffuse into the depletion region do so following an exponential time distribution [5]. Once the initial carrier is in the depletion region, the statistics of impact ionization will create a time uncertainty that is roughly a normal distribution. The overall timing response of a SPAD to a pulsed laser can be described as a background noise plus a normal distribution convolved with the addition of an impulse function (describing carriers generated in the depletion region) with an exponential distribution.

3 CMOS SPAD Design

Building SPADs in CMOS substrates requires knowledge of the process and layers available to the designer to implement junctions that can be reverse-biased at high voltages. Figure 2 shows a generic pn junction implemented in a planar process. The figure shows the depletion region, as it forms upon reverse biasing the junction (assuming a large doping differential between the p and n regions).
Fig. 2

Cross-sections of a generic pn junction in a planar process with the depletion region (gray line) forming in the structure upon reverse-biasing, assuming a large doping differential between the p and n regions

Implementing a pn junction in a planar process first involves finding a way to prevent premature edge breakdown (PEB). Several techniques exist to implement PEB prevention. In essence, the techniques have in common the reduction of the electric field or the increase of the breakdown voltage at the edges of the junction, so as to maximize the probability that the avalanche is initiated in the center of the multiplication region, i.e. the region where the critical electric field for impact ionization is reached and, possibly, exceeded.

Figure 3 illustrates four of the most used structures. In (a) the n+ layer maximizes the electric field in the middle of the diode. In (b) the lightly doped p- implant reduces the electric field at the edge of the p+ implant. In (c) a floating p implant locally increases the breakdown voltage. A polysilicon gate is usually drawn to prevent the creation of a shallow trench, however, it can also be used to further extend the depletion region.
Fig. 3

Cross-sections of doping profiles that may be used to prevent premature edge breakdown in planar processes

Shallow trench isolation (STI) can also be used to delimit the junction, provided that it is surrounded by a multi-layer of doped silicon so as to force recombination of those charges generated in the defect-rich STI as shown in structure (d) [6]. These structures are usually shaped as a ring around the junction; they are known as guard rings. Guard rings can also be defined implicitly by proper definition of drawn layers [7].

There exist a variety of avalanche quenching techniques, partitioned in active and passive methods. The literature on these variants is extensive [8]. In active methods, the avalanche is detected and stopped by acting on the bias. In passive methods the pn junction bias is self-adjusted e.g. by a ballast resistor. Recharge methods can also be active and passive. In active methods, the bias across the diode is re-established by a switch activated by an avalanche detector. In passive methods the recharge occurs through the ballast.

Upon photon detection, the device generates a current pulse that is converted to a digital voltage level by means of a pulse shaping circuitry, also shown in the figure. The pulse shaper is also acting as an impedance adapter to drive the load of the column readout often employed in a SPAD matrix.

The main parameters characterizing individual SPADs are sensitivity, measured as photon detection probability (PDP), noise, measured as the rate of spurious pulses due to thermal events or dark count rate (DCR). Other parameters include timing jitter, also known somewhat inappropriately as timing resolution, afterpulsing probability and the aforementioned dead time. These parameters have been used in the literature for a variety of CMOS processes [9, 10, 11, 12, 13, 14, 15, 16, 17].

When implemented in an array, other performance measures become relevant to the quality of the imager. Dead time uniformity relates to the variability in dead time, which determines the dynamic range of each detector. Timing jitter uniformity and PDP uniformity, as well as DCR uniformity and crosstalk have to be accounted for and properly characterized [9]. PDP of course will also be a function of the input wavelength. In CMOS SPAD implementations, the sensitivity range is mostly in the visible spectrum, with a somewhat reduced near infrared and near ultraviolet PDP.

Crosstalk is also a chip-level effect similar to PDP and DCR non-uniformities; it relates to the interaction between an aggressor pixel and a victim pixel, where the aggressor may cause a spurious avalanche in a victim. The effect can be electrical and/or optical. Electrical crosstalk is due to electrical interference through substrate or supply noise. Optical crosstalk may occur when an avalanche is triggered in the aggressor; by impact ionization, several photons may be emitted, thus causing the victim to detect them. While electrical crosstalk is strongly dependent on the design of supply lines and of substrate noise rejection measures, optical crosstalk may only be influenced by the number of carriers involved in an avalanche and by pixel pitch.

4 TCSPC Based TOF Camera Systems

Using TCSPC for optical rangefinding in D-TOF mode has been proposed several decades ago, since the introduction of the LIDAR concepts. SPAD based single-pixel detectors, in combination with scanning, powerful pulsed light sources. One of the first examples of this combination was proposed in [18, 19]. In this work, the light source is synchronized to the SPAD to produce an accurate evaluation of the Time-Of-Flight of the reflected photons and thereby of the distance to the target.

In [20] this concept was made scannerless thanks to the use of monolithic arrays of SPADs implemented in CMOS technology. The concept, described in Fig. 4, is enabled by the use of a cone of light reaching approximately simultaneously the target source.
Fig. 4

Time-correlated single-photon counting (TCSPC) for optical rangefinding and 3D imaging

The photons reflected by the surface are imaged through a lens system to the array. With the use of an accurate chronometer or stop watch, it is possible to derive the distance of the reflecting point using the following relation
$$ d \cong \frac{c}{2} \cdot \tau_{TOF} , $$
where τTOF is the Time-Of-Flight or the time difference between the light pulse synchronization signal and the time-of-arrival in the detector, and c is the speed of light in vacuum. Since SPADs are dynamic devices, they generate a digital pulse upon detection of a photon, and thus, unlike conventional diodes, they cannot hold a charge proportional to the overall photon count. Thus, the Time-Of-Flight must be computed in situ (either on pixel, on column, or on chip) or outside the image sensor. The same holds with integrated time-of-arrival evaluation: it can only be (1) in-pixel, (2) in-column, or (3) on-chip. To address this limitation, researchers have adopted a number of architectures that take advantage of the low propagation delay or high level of miniaturization achievable in standard submicron and deep-submicron CMOS technologies.
The simplest readout architecture implementing photon counting on-chip in combination with random-access single-photon detection, was demonstrated for the first time in a matrix of 32 × 32 pixels, each with an independent SPAD, a quenching mechanism, a pulse shaping and column access circuitry [20]. In this readout scheme, all time-sensitive operations had to be performed sequentially. This design has the main drawback in that it can only “see” one pixel at any point in time, while all the other pixels are operating but their output is lost. The micrograph of the chip is shown in Fig. 5; the chip was implemented in a 0.8 μm high-voltage CMOS process.
Fig. 5

The first large SPAD array with random access readout. The chip was implemented in 0.8 μm CMOS technology

Addressing the readout bottleneck required some degree of sharing. The column is the obvious place to start from, since it is a repetitive structure that touches all pixel rows. The first known such approach involved interpreting the column as a bus. The bus is used as transfer time and address over the same hardware. The time is coded in partially processed pulses generated in the pixel of which the time-of-arrival is evaluated. The address is coded as a unique combination over the lines present in the bus sent to the bottom of the column where the time-of-arrival is evaluated, either off or on chip [11].

The second approach, known as latchless pipelined readout, has a passive type of coding, whereas time-of-arrival also contain the information of the row position where the pulse was generated. Every photon triggers a pulse that is injected onto the pipeline at a precise location that corresponds to the physical place where the pixel is located. Since the propagation time is across the column is too short to enable any time-based discrimination, a timing-preserving delay line is added to the column. At the bottom of the column time discrimination is performed by a column-based TDC that also returns the row code [21]. The photomicrograph shown in Fig. 6 illustrates the actual implementation of the concept for a latchless pipelined 128 × 2 SPAD array fabricated in 0.35 μm CMOS.
Fig. 6

CMOS version of a latchless pipeline based readout fabricated in 0.35 μm CMOS technology [21]

An important step towards full parallelism was achieved with LASP [10], a 128 × 128 SPAD array, where a bank of 32 column-parallel time-to-digital converters (TDCs) was used to simultaneously process 128 in-line SPADs using an event-driven 4-to-1 column-multiplexer (one per column). Figure 7 shows the block diagram of LASP. Each TDC in the 32-array can generate 10 MS/s with a time resolution of 97 ps. The resolution can be further increased to 70 ps by acting on the clock frequency. Each TDC in LASP is a 3-tier partial TDC based on three different architectures: a clocked counter (2 MSBs, 25 ns resolution), a phase interpolator controlled by a temperature-compensated DLL (4 intermediate bits, 1.56 ns resolution), and a 16-taps Vernier line (4 LSBs, 97.6 ps resolution). The total time resolution of 10bits is routed outside the chip through a high-speed digital network operating at 3.2 Gb/s. The differential non-linearity (DNL) and integral non-linearity (INL) were recently improved to ±0.1LSB and ±0.25LSB, respectively [22].
Fig. 7

Schematic and micrograph of LASP; an array of 32 TDCs processes the pulses generated by 128 SPADs at any time by means of a 4-to-1 event-driven multiplexer (one for each TDC)

The chip was tested in TCSPC mode to compute a scene’s depth via a pixel-by-pixel Time-Of-Flight evaluation of a defocused beam hitting the target. The results of the experiment are shown in the histogram of Fig. 8. The jitter is dominated by the SPAD timing uncertainty, whereas the characteristic tail of the device also appears from the picture.
Fig. 8

TCSPC experiment. The laser pulse is pointed toward a SPAD in the array and the time-of-arrival of the first detected photon is evaluated by the corresponding TDC. The resulting histogram, shown in the plot in logarithmic scale, is then computed [10]

The distance evaluation result is shown in Fig. 9 as a function of the real distance measured using a precision device from 40 cm to 3.75 m. Each distance measurement was derived from the centroid of the corresponding histogram, whereas the uncertainty as a function of distance is plotted in also plotted in the figure.
Fig. 9

Actual distance versus estimated distance computed in LASP at room temperature (top); average error versus distance (middle); standard deviation versus distance (bottom) [10]

In Fig. 10 the resulting 3D image of a mannequin illuminated by a cone of pulsed laser light with a wavelength of 637 nm is shown after a 1 s exposure. The 3D points represent the centroid of the histograms of each pixel.
Fig. 10

Target image computed by LASP in 1 s exposure at room temperature [10]

The integration of time-resolving electronics on a per-column or per-chip basis represents a trade-off between fill-factor, processing bandwidth and circuit area. Unlike integrating image sensors based on photodiodes, photons falling on SPAD pixels which are not multiplexed to available time-resolving channels are lost. In an efficient SPAD sensor operating in D-TOF mode, a time-stamp must be generated for every impinging photon at every pixel detector. This necessitates the combination of per-pixel time-digitization circuitry and high speed array readout.

The integration of a large array of in-pixel TDCs or time-to-amplitude converters (TACs) poses several challenges with respect to single channel architectures found in the literature [23, 24, 25, 26]:
  1. 1.

    Circuit area is limited to a few 100 μm2 to achieve practical pixel fill-factor and pitch.

  2. 2.

    Power consumption cannot exceed a few 100 μA per pixel, in order to allow array size to be scaled to 10’s of kilopixels without excessive heating.

  3. 3.

    Uniformity requires around 1 percent matching of time resolution for acceptable image quality without requiring a frame store for pixel calibration.

  4. 4.

    Throughput must assure conversion of photon arrivals within typical pulsed illumination period of 100’s of nanoseconds to avoid statistical distortions leading to non-linearity.

  5. 5.

    Time resolution is required to be a few 10’s picoseconds in a full-scale range of around 25–50 ns resolution for indoor applications where human body features are to be distinguished at a maximum distance of a few meters.

These stringent specifications discount many of the conventional TDC architectures which achieve sub gate-delay resolution. Two scalable in-pixel TDC approaches were proposed in [27] and [28], differing by the adoption of an internal clock (IC-TDC) or an external clock (EC-TDC) as a source of timing accuracy (Fig. 11). Both converters operate in reverse START-STOP mode whereby they are started by a photon detected by the SPAD front-end circuit and stopped by a global clock synchronous with the pulsed optical source.
Fig. 11

Time-to-digital conversion pixels: a external clock b internal clock

The IC-TDC integrates a gigahertz gated ring oscillator within each pixel, which clocks an n-bit ripple counter providing coarse photon arrival time estimates. Fine time estimates are obtained by decoding the frozen internal state of the ring providing the 3 least significant bits, which represent single inverter delays. A four-stage differential ring oscillator is chosen with a binary number of internal states for simplicity of decoding logic. Two implementations have been studied, a chain of tri-stateable inverters provide static internal state memory [29] while the second, a chain of inverters connected by pass-gates provide a dynamic internal state memory [27]. Care must be taken to avoid metastability when gating the ring oscillator clock to the ripple counter, by employing hysteresis in the clock input stage. Tuning of the ring oscillator loop delay is achieved by current starving the differential inverters through a NMOS regulating transistor. This is also effective in diminishing the effect of supply noise induced jitter. IC-TDCs have the advantage of consuming power only when activated by an impinging photon, thus the power consumption of a large array is directly proportional to photon flux. This in turn has the potential disadvantage of introducing a light-flux-dependency of the TDC resolution, due to variable IR drops.

The EC-TDC achieves coarse time measurement in the similar manner to the IC-TDC, by means of an n-bit counter, clocked by an external high frequency clock distributed to the entire pixel array. Fine resolution is determined by the propagation delay of the SPAD pulse through an inverter chain. The state of inverter chain is frozen by the subsequent rising edge of the clock that is synchronized with the STOP signal and decode logic converts the thermometer code into a k-bit binary number. The STOP signal also halts the coarse counter. Time resolution calibration is performed by current-starving the inverter chain, through a feedback loop [28]. EC-TDCs consume an almost constant power level irrespective of input illumination but provide good global time resolution accuracy and negligible resolution dependency on photon flux.

Scaling of the per-pixel TDC approach from early prototypes of 32 × 32 to 160 × 128 pixels has been demonstrated with good performance. Characterization of a large IC-TDC image array has shown good DNL, INL, and pixel-to-pixel uniformity [29].

In Fig. 12, a TOF experiment is conducted for a single column of pixels, using a pulsed laser at a constant distance from the sensor. Future implementations of these architectures in advanced nanoscale CMOS technologies bring the prospect of considerable gains in fill factor, time resolution, power consumption, and pixel pitch.
Fig. 12

Time of flight measurements with IC-TDC array

Figure 13 shows an analog approach to per-pixel time estimation, employing an in-pixel TAC and ADC converter [30]. A current source (IbiasP) charges a capacitor Cs when the switch-structure, composed of Mp1, Mp2, Mp3, and IbiasN, is enabled. Three layout-matched replicas of the ramp-generator building block are employed: Stage1 and Stage2 are used alternately to measure the number of events or the event arrival time in a time interleaved way as Vo1 (or Vo2); StageREF is used to generate a reference voltage ramp VoREF for the embedded single-slope ADC. Analog time encoding is started on detection of a photon, by the charging of capacitor Cs, and stopped by the subsequent STOP clock rising edge. At the end of this interval, a voltage has accumulated on capacitor Cs that is proportional to the photon arrival time.
Fig. 13

Time-to-amplitude converter pixel architecture

After an exposure time, the pixel array is switched over to analogue to digital conversion mode. The clock signal CNT and an n-bit Gray code count sequence operate synchronously and are globally distributed to the pixel array. The StageREF block generates a stepped analog ramp voltage VoREF, which is compared to Vo1 (or Vo2) by an in-pixel comparator. When VoREF exceeds Vo1 (or Vo2) the voltage comparator toggles, sampling the Gray code into the memory. Hence the stored value of the Gray code is directly proportional to the analog voltage determined previously by the time-to-analog conversion process. Two memories are employed to allow one to participate in conversion while the other is being read-out. While the performance of the per-pixel TAC array was less favorable than the TDC counterparts (Table 1), this architecture shows greater promise in terms of scaling for area and power without the need for advanced nanoscale CMOS technology.
Table 1

Performance comparison of per-pixel TAC/TDC arrays


TAC [30]

TDC-EC [28]

TDC-IC [27]


Technology node





Pixel pitch





Bit resolution





Time resolution (LSB)




















Time jitter




ps @ FWHM

Power consumption




μW @ 500kframe/sec

Highly parallel readout schemes must be employed to handle the extremely high volumes of per-pixel timestamp data generated by both per-pixel TDC and TAC image arrays. Single-photon detectors produce events at each pixel at much greater rates than conventional integrating image sensors, especially those generated by ambient lighting or DCR distribution. Data rates of several Gbps have been attained in recent imagers [29, 31].

Per-pixel time-resolving arrays, which integrated the TAC/TDC in same CMOS substrate as the SPAD detector face, have two practical drawbacks:
  1. 1.

    The bandgap of silicon limits detection to wavelengths below 1125 nm. Common CMOS SPADs have poor PDP (below 5 %) at suitable NIR wavelengths (850 or 930 nm) due to the shallow active junction.

  2. 2.

    The pixel fill factor is low due to the large insensitive area devoted to the time-resolving electronics; around 1–2 % have been demonstrated in the above research.


Hybrid 3D wafer technology offers a solution to this dilemma. Itzler et al. [32] have developed InGaAs/InP avalanche diode structures in the wavelength range of 0.92 to 1.67 μm, which are hybridized to CMOS read-out integrated circuits (ROICs) that enable independent laser radar Time-Of-Flight measurements for each pixel. The 9 % fill-factor of the SPAD array is improved to 75 % by employing a micro lens array and an average photon detection efficiency (PDE3) of 39 % is obtained. The ROIC consists of an array of 100 μm pitch pixels containing pseudorandom counters in a 0.18 μm CMOS process clocked from an external PLL distributed to all pixels. The power consumption of the array is only 50 mW at 20 kHz frame rate and 320 mW at 200 kHz. Aull et al. reported a similar 64 × 64, 50 μm pitch ROIC in 0.18 μm CMOS for a similar 3D stacked technology with a time resolution of 110 ps [33].

5 Single-Photon Synchronous Detection

The technique known as single-photon synchronous detection (SPSD) is an I-TOF measurement, the SPAD-digital equivalent of lock-in detection [34, 35, 36, 37, 38]. In SPSD, proposed for the first time in [39], the scene is illuminated with a sinusoidal or pseudo-sinusoidal light intensity and the phase of the return photons. As in lock-in systems, distance d is computed as
$$ d \cong \frac{c \varphi }{{2 \cdot 2\pi f_{0} }}, $$
where c is the speed of light in vacuum, f 0 is the modulation frequency, and φ is the measured phase difference between outgoing signal and measured signal. In SPSD, unlike in lock-in systems, the phase φ is computed directly by counting photons in a structured way.
In SPSD the period of the illumination is discretized in N C uniform time segments ΔT 0, ΔT 1,…, ΔT k,…, Δ\({T_{N_{C-1}}}\). At the end of the integration period, every counter stores a value C k, corresponding to the counted photons in the time period ΔT k during the integration period. For each segment the SPAD’s output is directed to a counter that is activated only during that segment, the photon counter results C k. shows how the illumination source is modulated and discretized. The figure also shows how the SPAD’s output is distributed to the various counters to generate C 0 through \({C_{N_{C-1}}}\)in a possible block diagram implementation of the technique on pixel (Fig. 14).
Fig. 14

Possible discretization of a period of illumination, with resulting partial counts (left); block diagram of the pixel in an SPSD camera as described in [39] (right)

For the case N C = 4, with only four partial counters C 0, C 1, C 2 and C 3, the phase becomes
$$ \varphi = \arctan \left( {\frac{{C_{3} - C_{1} }}{{C_{0} - C_{2} }}} \right). $$
As a byproduct of this computation we also achieve an estimate of the offset and amplitude of the illumination intensity, as
$$ \begin{gathered} A^{\prime} = \frac{{\left( {C_{3} - C_{1} } \right)^{2} + \left( {C_{0} - C_{2} } \right)^{2} }}{2}; \hfill \\ B^{\prime} = \frac{{C_{0} + C_{1} + C_{2} + C_{3} }}{4}. \hfill \\ \end{gathered} $$
The parameters A′ and B′ are illustrated in Fig. 15 which shows a sequence of photon detection where the partial counts are progressively building up the waveform corresponding to a single period by superimposing adjacent measurements, thus enabling the computation of phase, offset, and amplitude.
Fig. 15

Principle of operation of SPSD cameras. Impinging photons are detected and “assigned” to the appropriate bin depending upon the time-of-arrival with respect to the outgoing optical signal

A SPSD image sensor based on the concept outlined in Fig. 15 was implemented in an array of 60 × 48 pixels operating in real-time with an integration period as low as 10 ms and a frame rate as high as 100fps. A block diagram and a photomicrograph of the image sensor is shown in Fig. 16, whereas the pixel in this design comprises two 8-bit counters to compute alternatively C0/C2 and C1/C3. The pixel has a pitch of 85 μm and a fill factor of 1%, which can be compensated to a partial extent by the use of a microlens array [40].
Fig. 16

Block diagram (left) and photomicrograph of the SPSD image sensor (right) proposed in [39] for the first time and fabricated in 0.35 μm CMOS technology

The chip was used in several experiments to test its robustness to ambient light and interferences. The illuminator used was an array of 48 850 nm LEDs (Osram GmBH, Germany) located in three concentric circles as shown in Fig. 17.
Fig. 17

Illuminator used in combination with the integrated SPSD image sensor. The total optical power emitted by the illuminator is 800 mW. The frequency of operation is 30 MHz, with a 3rd harmonic component suppressed at 37 dB

The plots shown in Fig. 18 show the estimated distance versus the actual distance measured in a similar distance range as in the TCSPC experiments. The figure also shows mean errors and standard deviations as a function of the distance.
Fig. 18

Estimated versus actual distance using a SPSD pixel (top). Mean error versus distance (middle) and standard deviation of the error versus distance (bottom). All the data are reported at room temperature [39]

The same mannequin used in LASP was also used in the SPSD experiments. The results confirmed the estimated error. Figures 19 and 20 show a target at two exposure times, evidencing the relation between exposure, or number of the counting iterations, and overall distance error at the pixel level.
Fig. 19

3D image of mannequin in real-time exposure (30fps) at room temperature [39] at a different integration times

Fig. 20

Target image computed by SPSD in real-time exposure (30fps) at a shorter (50 ms) and longer (500 ms) integration times

The images show the expected dependency of accuracy from exposure time. This behavior can be quantitatively analyzed looking at the demodulation contrast. Let us consider the statistical error of the distance measurement,
$$ \sigma_{Error} = \frac{c}{{2 \cdot 2\pi f_{0} }}\sigma_{\varphi } , $$
where σφ is the standard deviation of the phase measured using SPSD. Assuming NC = 4, Eq. (6) can be rewritten in terms of the illumination parameters, as
$$ \sigma_{Error} = \frac{{R_{D} }}{\sqrt 8 \pi }\frac{{\sqrt {B^{\prime}} }}{{A^{\prime}}}, {\text{with}} \,R_{D} = \frac{c}{{2f_{0} }}. $$
Rearranging the terms and substituting, we obtain the following equality
$$ \sigma_{Error} \cong \frac{{R_{D} }}{{\sqrt 8 \pi c_{D} }}\frac{1}{{\sqrt {T \cdot SBR \cdot S_{R} } }}, $$
where T is the integration period, SBR is the signal-to-background ratio, and S R is the signal count rate (the sum of all counters) on the image sensor. The term c D is known as demodulation contrast, defined as
$$ c_{D} = sinc\left( {\pi \frac{\Updelta T}{{T_{0} }}} \right), $$
where ΔT is the mean time segment duration, in this case ¼ of the total modulation period T 0 = 1/f 0. In this configuration, the demodulation contrast is 0.9, whereas 1.0 is the maximum achievable value. By increasing the number of samples to, say 8, the demodulation contrast would only increase to 0.974, but at a cost extra hardware and thus fill factor. Also note that the actual demodulation contrast decreases with modulation frequency. However, in SPSD it reduces very slowly while in lock-in systems it quickly degrades due to the limits in transit time in the pixels. The plot of Fig. 21 shows the relation between the demodulation contrast and the availability of the signal S R, as the target is further and the Time-Of-Flight increases.
Fig. 21

Measured demodulation contrast as a function of distance in SPSD at room temperature [39]

6 Phase-Domain Delta-Sigma TOF Imaging

As has been discussed, phase-demodulating systems typically generate two or more bin values per frame requiring readout and external processing in order to produce a depth map. This IO and processing burden can result in a significant portion of the complete system’s power consumption and computational load. Recent trends have seen an increasing level of complexity integrated into the sensor’s focal plane to boost acquisition speed and reduce the required external circuitry. For example, while the first TOF 3D imaging systems were based on scanned single point range sensors comprising a discrete APD and external time-stamping circuitry, recent sensors have combined arrays of SPADs with on-chip time-stamping or binning logic, such as the TDC and SPSD systems discussed earlier in this chapter.

A natural extension of this theme of integration is the use of modern CMOS processes to construct sensors with additional focal-plane logic to allow the on-chip creation of depth-maps, reducing the IO and external processing needs of such systems. One such approach is to place a Phase-Domain Delta-Sigma (PDΔΣ) loop in the pixel. Figure 22 below compares the architecture of a simple ΔΣ ADC with its phase-domain equivalent. While the ΔΣ ADC measures the magnitude of an input voltage with respect to two reference voltages, the phase-domain implementation instead measures the mean phase of its input with respect to a pair of reference phases. This approach has been successfully demonstrated in applications including magnetic flux [41] and temperature [42] sensing, where the particular sensing elements used created a phase shift in response to the property to be measured.
Fig. 22

Comparison of: conventional ΔΣ ADC (top), phase-domain ΔΣ converter for 3D imaging (bottom)

I-TOF 3D imaging systems also of course depend on the measurement of a phase shift. Crucially, an all-digital PDΔΣ loop may be constructed which locally processes the SPAD pulses created within a pixel and converges to estimate this depth related phase shift directly. This approach was employed in the 128 × 96 pixel sensor reported in [31], as illustrated in the architecture block diagram and die micrograph shown in Figs. 23 and 24 below.
Fig. 23

Architecture of 128 × 96 pixel, all-digital, phase-domain ΔΣ based sensor reported in [31]

Fig. 24

Die micrograph of 128 × 96 pixel, all-digital, phase-domain ΔΣ based sensor reported in [31]

The loop operates in a similar fashion to existing two-bin demodulating approaches [43], dividing the returning pulse energy into two bins: in phase and 180° out of phase with the transmitted modulated light. However, instead of simply integrating the energy in these bins over a period of time and transmitting their contents for external processing, the loop continually seeks to drive its internal integrator towards zero by integrating positively during φ1 and negatively during φ2, as the timing diagram contained in Fig. 25 below illustrates. The resulting bitstream density, r, indicates the mean phase of the input pulses, as governed by Eq. 10, where N φ1 and N φ2 represent the number of photons counted in bins φ1 and φ2 respectively.
$$ r = \frac{{N_{{\phi_{2} }} }}{{N_{{\phi_{1} }} + N_{{\phi_{2} }} }} $$
Fig. 25

Timing diagram of all-digital, phase-domain ΔΣ based pixel [31]

This calculation is of course influenced by the DC component of the detected light, which must be corrected, for example by subtracting the DC component from each bin value using an integration of equal exposure time with the illumination source disabled.

Characterization data for the PDΔΣ, including INL and repeatability error characterization was presented in [31]. Relatively low illumination power and pulse rates were used at the expense of repeatability error. However, the PDΔΣ approach achieved an excellent linearity of ±5 mm over a 0.4–2.4 m range, with photon pile up being the dominant effect limiting accuracy at very short distances.

Figure 26 shows example images captured using the PDΔΣ sensor, serving as the first demonstration of the on-chip creation of depth-maps with only simple inter-frame averaging and defect correction being applied externally before rendering.
Fig. 26

Example images captured using PDΔΣ sensor [31]: a 20 second exposure showing mannequin at 1m distance. b 1 second exposure showing objects at 0.75m, 1.1m, and 1.8m

The use of an in-pixel, phase-domain ΔΣ loop to directly sense the mean phase of incident photons detected synchronously to the modulation of the outgoing illumination light is one approach to the management of the large volumes of data produced by single-photon 3D imagers and the associated computational burden on the host system. With the increasing commercial relevance of 3D imaging systems, such techniques seem likely to continue to develop, facilitated by the capabilities of modern CMOS imaging processes to yield highly integrated imaging systems.

7 Perspectives and Outlook

More recently, scanned 3D cameras have appeared based on relatively small arrays of relatively large pixels whose core is a so-called silicon photomultiplier (SiPM). SiPMs are essentially an array of non-imaged SPADs connected so as to sum all avalanche currents in one point. The more recent digital SiPM replaces the analog summing node with an OR operation. The advantage of d-SiPMs is a faster response to photon bunches and the capability of turning off individual noisy SPADs. An example of this trend has been reported by [44], where four 10 × 10 mini SiPMs have been implemented in 0.18 μm HV CMOS technology in combination with a mirror to scan large areas in TCSPC mode.

The use of mini SiPMs is spreading to other fields and applications. An example is that of medical sensors for positron emission tomography that rely on time-of-arrival detection. Borrowing technologies developed in 3D camera technology, more TDC integration together with SPADs and SPAD arrays is a clear trend.

Recent SPAD structures demonstrated in nanoscale CMOS exhibit improving DCR and spectral efficiency, as well as compatibility with TSV and backside processing [45, 46, 47]. Adoption of these advanced processes brings the prospect of simultaneous improvements in time resolution, fill factor, pixel pitch as well as the capacity to integrate on-chip Time-Of-Flight computation to ease I/O data rate demands. Analog approaches to time-resolved SPAD pixels offer a route to the smallest pixel pitch provided uniformity issues are addressed [48].

On another front, the emergence of III-V materials in configurations that are fully compatible with a CMOS fabrication line may bring these materials to the mainstream in 3D imaging. Examples of this trend are two independent works reporting the first Ge-on-Si SPADs fabricated in a way that is fully compatible with a conventional CMOS technology [49, 50]. More activity in this domain is expected, especially in the creation of larger and more compact arrays.

Finally, 3D integration of CMOS devices is becoming a commercial reality, hence, we expect that it will extend to 3D image sensors based on SPADs where through silicon via and backside illuminated devices will become routine in the near future. This will have an immediate impact on fill factor and imager sizes. Later cost will be positively impacted and packaging simplified.


  1. 1.

    The preposition “above” is used because researchers working with APDs consider the cathode to be the terminal with the higher voltage.

  2. 2.

    Termed after the similarity to a Geiger counter.

  3. 3.

    PDE is defined as the multiplication of fill facto and PDP.



The authors are grateful to the Swiss National Science Foundation, the Swiss Government sponsored Nano-Tera and MICS grants, and Xilinx Inc.’s University Program.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Edoardo Charbon
    • 1
  • Matt Fishburn
    • 1
  • Richard Walker
    • 2
  • Robert K. Henderson
    • 2
  • Cristiano Niclass
    • 3
  1. 1.TU DelftDelftThe Netherlands
  2. 2.The University of EdinburghEdinburghScotland, U.K
  3. 3.EPFLLausanneSwitzerland

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