Post-silicon Speed-Path Analysis in Modern Microprocessors through Genetic Programming

  • Ernesto Sanchez
  • Giovanni Squillero
  • Alberto Tonda
Part of the Intelligent Systems Reference Library book series (ISRL, volume 34)

Abstract

The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Nowadays, comprehensive verification of a chip can only be performed after tape-out, when the first silicon prototypes are available. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating to this post-silicon time as well. This chapter describes a post-silicon methodology that can be exploited to devise functional failing tests. Such tests are essential to analyze and debug speed paths during verification, speed-stepping, and other critical activities. The proposed methodology is based on the Genetic Programming paradigm, and exploits a versatile toolkit named μGP. The chapter describes how an evolutionary algorithm can successfully tackle a significant and still open industrial problem. Moreover, it shows how to take into account complex hardware characteristics and architectural details of such complex devices. The experimental evaluation clearly demonstrate the potential of this line of research. Results of this work have been accepted for publication in [137].

Keywords

Genetic Programming Automatic Test Equipment Automatic Test Pattern Generator SIMD Instruction Incorrect Behavior 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Ernesto Sanchez
    • Giovanni Squillero
      • Alberto Tonda

        There are no affiliations available

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